This thread initially related to KCPSM6 being used on a Spartan-6. You are using KCPSM3, UART macros along with your own logic and PicoBlaze program on a Spartan-3 so try not to be too quick jumping to conclusions about the cause of your failure. That said, there does appear to be a small trail of cases in which the use of any optimisation setting other than ‘Off’ has caused issues so that is a worthwhile avenue to explore.
However, if setting to ‘Off’ isn’t helping then it makes me suspicious that you may have a timing issue of some kind in your design. That would probably not show itself in a pre-implementation simulation. As with the previous discussions contained in this thread, the use of a post-implementation simulation may isolate the issue. A genuine functional difference due to incorrect MAP should be pretty obvious but you would have to be careful to confirm that any failure wasn’t caused by a timing issue. From my experience, timing simulation has often be the cause of confusion. A simulation is only as good as the vectors applied to it and they tend to be rather too perfect. The timing delays may be worse case but again all rather fixed in relation with each other and real silicon isn’t like that.
If you really have encountered an issue with the ISE tools then do open an official case with Technical Support.
Ken Chapman
Principal Engineer, Xilinx UK
