07-21-2010 07:27 AM
Well I think I have this figured out. Here is what I did in case this helps anyone or I missed something obvious. I'm running 11.4. Bit puzzled about comments in the code about different syntax for ISE 12.
For the ROM. Used the VHDL Template and had Mediatronix fill it in. We use a make workflow for build.
Best way I found to to integrate it, without a lot of messing around for a single language Sim was to black box it in the Verilog.
Added a separate make entry to have XST build an small .ngc of the ROM and jtag, if any of the VHDL changes. This is a lot like the way Chipscope gets integrated.
For the JTAG flow I have Mediatronix make a .mem file. Wrote a simple bit of C to turn this into a hex file and the stuffed that into Kens TCL. I fire the whole process off the build using a .bat file when mediatronix exectutes. There is TCL source so it may be easier to hack that to take a .mem but I already had code to read the .mem. .