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kcpsm6 UART6 overlayed output
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04-02-2012 10:15 AM
Following guide of UART6 to port on a Digilent Atlys Spartan6 board I obtain an overlayed output in the serial terminal (putty, hyperterminal, ...), the final mesagge is:
and the correct output would be:
I don't find many differences between the example provided for ML605 (Virtex6) and my Atlys (Spartan6) except pins and prog_rom parameters, this is my configuration in Verilog:
prog_rom #(
.C_FAMILY ("S6"), //Family 'S6', 'V6' or '7S'
.C_RAM_SIZE_KWORDS (2), //Program size '1', '2' or '4'
.C_JTAG_LOADER_ENABLE (0)) // NO! Include JTAG Loader, NO! support yet for Atlys
rom ( //Name to match your PSM file
.rdl (rdl),
.enable (bram_enable),
.address (address),
.instruction (instruction),
.clk (clk));
Any experiences in this way? Any suggestions? I've revised many time the code and I don't find reference designs for kcpsm6 and uart6 on spartan6.
I'm desperate!
Thanks in advance
-- josan
Re: kcpsm6 UART6 overlayed output
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04-02-2012 11:49 PM
Hi Josan,
there may be many causes for this error.
What is your Picoblaze sending to terminate a line?
Just <CR> or <LF> or both?
And how is your terminal setting?
There are sometimes options for "Automatic LF on CR" and similar stuff.
Check it.
Actually your data is printed down to the "> " prompt.
So there can just be some mismatch between the line termination methiods of your Picoblaze and the terminal.
Have a nice synthesis
Eilert
Re: kcpsm6 UART6 overlayed output
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04-03-2012 03:26 AM
Eilert is almost certainly correct. The example code provided with KCPSM6 only outputs carriage return characters (0D hex) at the end of lines. HyperTerminal has an ASCII set up option called something like ‘Append Line Feeds to Carriage Returns’ so thy that or whatever the equivalent is in your terminal. Alternatively, adjust the PicoBlaze code to also send a line feed character (0A hex) at the end of each line.
Principal Engineer, Xilinx UK
Re: kcpsm6 UART6 overlayed output
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04-03-2012 12:33 PM
Thank you Eirlert and Ken, I have solved adding line feed 0Ah at lines finally. I would want to make a reference design for my board (Digilent Altys) before starting the app, but it's very hard without jtagloader in this board for debugging. I'm novice with PB but I have got to r/w gpio and adjust baud rate comp for my clk at 100MHz in 9600pbs.
Thanks again. Best regards











