Simulation and Verification

[asrock70]

Such a rudimentary question.

For CPLD have very simple design only one ExclusiveOR gate in  VHDL Out <= In1 xor In2.

My question.

How do I know  (how simulate) the smallest pulse may occur at the output ?

In other words, what are the limits of hardware ExOR gates in examples CLPD XL9536 10ns

Thansk

[edv]

Hi asrock,

You can test the performance limits of the macrocell I/O by running a timing simulation.  In this flow, the simulation is back-annotated with timing delay maximums so you can observe the expected hardware behavior against the input stimuli.

Alternatively, you can look up the internal timing parameters for the XC9536XL part in the datasheet.  A combination of these parameters (combinatorial delay, register setup time, register clock to output valid time) play a role in what would be the shortest pulse the output can generate.

Hope this helps.