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Visitor
kmacc
Posts: 5
Registered: ‎06-23-2009
0

Changing register value during simulation

Hi,

 

I've been trying to alter the value of a register during a simulation. I tried the "put" command in the console but it didn't seem to have an effect.

 

Is this sort of thing possible?

 

Cheers,

 

Kenneth.

Expert Contributor
gszakacs
Posts: 5,269
Registered: ‎08-14-2007
0

Re: Changing register value during simulation

If you're using ModelSim the command you want is "force".
-- Gabor
Expert Contributor
eilert
Posts: 2,064
Registered: ‎08-14-2007
0

Re: Changing register value during simulation

Hi Kenneth,

The 'put' command belogs to ISIM, and works similar to the Modelsim 'force' command.

You have to make sure that it doesn't conflict with other datasources for that register (eg. testbench)

and that you release the assignment after some time to see the behaviour of your register again.

(I think there is a 'release' command in Modelsim for that purpose)

 

Anyway, why do you want to alter the register contentas *during* a simulation?

Are you trying to simulate spurious errors like what's caused by radiation, ore something similar?

Even then I would recommend to expand your models with the ability for such simulations using the 'synthesis_off' and 'synthesis_on' pragmas.

 

Have a nice simulation

  Eilert

Regular Visitor
kdeepak
Posts: 25
Registered: ‎06-24-2009
0

Re: Changing register value during simulation

Dear ISim User,

 

If you want to temporarily change value of a VHDL signal/Verilog wire, VHDL process variable, or Verilog reg, then you can use ISim's put command. The put command changes value of a VHDL signal, VHDL process variable, Verilog reg or Verilog wire to the specified value at the time of execution of the put command. However, if the user's HDL code makes any assignment later on during simulation, the value deposited by the put gets overwritten by the user's HDL assignment. So, put command is somewhat like force -deposit ModelSim Do command.

 

On the other hand, if you want to force value of a VHDL signal or Verilog wire (VHDL process variable and Verilog reg are not allowed to be forced using Tcl in ISim) to a particular value so that any assignment made to the forced signal/wire in user's HDL does not have any effect until the signal/wire is unforced, then you should use isim force command. ISim's isim force is somewhat like force -freeze ModelSim Do command.

 

PS: To learn more about DO command compatibility of ISim Tcl commands, open ISim User Guide  http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/plugin_ism.pdf and expand Appendix Reference and then click on Third-Party Tcl Commands. To learn more about put and isim force command search them in the ISim User Guide.

 

HTH,

Kumar

-- Kumar Deepak
Xilinx Inc.