Hardware Co-Simulation "Wait For FPGA"

julius.sch · ‎10-31-2011

Dear forum,

I need to do a hardwatre co-simulation. Therefore I have some part of a simulation in simulink and another part implemented on the FPGA. I like to know if it is possible, to calculate the simulink part, then transfer some results to the FPGA and return some vaules back to simulink (at every time step). To do so, I need to stop the simulation in Simulink until the FPGA has finished its calculation and returns the results. Does anyone know, who this can be realized?

Best,

Julius

eilert · ‎08-14-2007

Hi Julius,

not quite sure what the problem is.

What you describe is done automatically by the System Generator HW-Cosim environment.

You can have a synthesized HW-Cosim block and then some Xilinx-Blockset stuff or simulink blocks around it, even Blackboxes that do SW-Cosimulation with some HDL sources in the meanwhile.

Have a nice simulation

Eilert

julius.sch · ‎10-31-2011

Hi Eilert,

please excuse my late reply.

When I start a simulation, Simulink upadtes are done in increments of seconds. Each block in the path will delay the result. (Register by 1 second, Multiplication by 3 seconds.) I want the time base of the FPGA to be independent of the Simulink time steps. The result should be passed in the same time step.

Simulink starts the calculation, waits until the FPGA has calculated the results and assumes it in the same time step.

Best,

Julius

eilert · ‎08-14-2007

Hi Julius,

does it really wait that second in HW? WOW. Maybe I never experienced this, because I never used this default setting in HW-Cosim. But it makes sense. If you(r design) demand(s) it, FPGA will do it.

Now, it's quite simple to overcome this, and you should do this as well for normal simulations, in order to get meaningful time information for your signals. Honestly, 1s sampling rate? What system can use that?

Solution:

Set the Simulink Period in the System Generator block to some reasonable value. (Which depends on your design specification, in extreme it's the FPGA-Clock e.g. 20e-9 for a 50 MHZ clock)

Also set the sampling times for the Gateway In blocks to that value, and it may be necessary to be applied to most of your synchronous blocks as well to be on the save side. Some may inherit the input sampling time some not. Check it.

My way of dealing with Sysgen simulations is to write a matlab script which generates all settings and input data and then uses the sim command to start the simulation.

In that script i use a variable named "period" to derive all necessary timing from.

So most of the blocks have "period" in ther sampling time parameter field,

and for the simulation time I use "period * (length(t)+latency_offset)"

Thus the model and simulation time is under full controll of the script, and timing changes are done in an instant. Otherwise iou have to change many parameters and are doomed to forget one or another stumbling from one faulty simulation to another.

Have a nice simulation

Eilert

julius.sch · ‎10-31-2011

Hi Eilert,

thank you for your detailed answer!

Yes, the step size is actually a second, just because Simulink starts only every second to calculate.

When I enter a step size of 1e-3, everything works. At 10e-5, I get an error message. He can not find the synthesis tool?!?

Can the free-running clock mode solves my problem? Have you ever used this mode and you could tell me how it works?
I think in free running mode Simulink is waiting until one of the outputs has changed its state. That would be exactly what I want Simulink to do.

Julius

julius.sch · ‎10-31-2011

Begin generation
Checking model status
Checking simulation times
Performing compilation and generation
Compilation and generation completed in 12.8622 seconds
ERROR:HWCoSim - Failed to find Dictionary key: "synthesisTool"

*** ERROR ***

Hardware co-simulation compilation failed. Failed to find Dictionary key: "synthesisTool"

eilert · ‎08-14-2007

Hi Julius,

Free running mode just gives you other problems.

First of all, your design needs to be changed almost completely, if that mode applies fpor your application at all.

This mode is mainly made for designs that interact with external hardware, and have only some status registers that can be written or read without disturbing the activity of the design.

The error message you get is also under discussion in other treads.

e.g. this one:

http://forums.xilinx.com/t5/DSP-Tools/hwcosim-error-Dictionary-key-quot-empty-quot/m-p/193670

Please read these and see what comes up. Myabe you find a solution there.

Basically working with a 10kHz sample rate is no big deal for HW-Cosim, so something else must be the cause for this error.

Have a nice simulation

Eilert

julius.sch · ‎10-31-2011

Hi Eilert,

the cause of this error is not located in the model. It seems to be a system-generator bug, if step sizes of 10e-5 are generally possible. A simple model which contains only one register caused the error also. I add the simple model and the model, I'm actually working on, to this post.

In my model a longer calculation, which requires 50 time steps, is performed. When I run the simulation in single-steped mode 49 input values are lost. I want to avoid this! Can this be achieved in the free-running mode?

Perhaps you can give me a simple example-model, which is running in free-running clock mode?

Best regards,
Julius

fruntxas · ‎10-07-2009

Hi Julius,

Did you have any luck with the "Failed to find Dictionary Key" problem?
I also have a "double layer" design. One layer to be kept in Simulink and another to cosimulate but can't avoid this error apparently :(