Simulation and Verification

[olufola]

Hi all,

I keep on getting an error that makes it appear as if certain names cannot be used for Verilog modules for design targetting Virtex6 in ISE 13.4. The exact error message is:

ERROR:NgdBuild:605 - logical root block 'CyclicBench' with type 'CyclicBench' is
unexpanded. Symbol 'CyclicBench' is not supported in target 'virtex6'.

I don't know how to get around this problem.

[sushantm]

It means you are using a module called 'CyclicBench' that isn't resolved and isn't a device primitive when it runs ngdbuild.

The likely cause is either:

-this module is RTL source and you haven't synthesized it so it is a black box

-this is a netlist and ngdbuild can't find it:

kindly refer http://www.xilinx.com/support/answers/11701.htm

Let me know how it goes.

[olufola]

Thanks.
The module is a RTL source but I get the same error when I tried to synthesize the module. It was the "Check Syntax" process that gave the error initially.

[sushantm]

Did you check the avove link ?

It seems like tool didnt find your module's edif/ngc/... for your rtl source.

Are you using IP from Core gen ?

Or using your own then provide ngc path in MACro search directories

Follow

To avoid this problem, verify that the module description file has the correct name and is located in the macro search path or project directory.
To set the macro search path, following these steps in ISE: 1. Select the top-level source in the Source window. 2. Right-click "Implementation Process" in the Process window and select "Properties." 3. Select the "Translate Properties tab." The Macro Search Path option is available.

[olufola]

Yes. I checked the link. The source is my own Verilog code. I have just a single file containing the module and the test bench are both are already included in the project. I don't think it is a macro search path problem. I have been avoiding the use of ISE until now because of this error until I hit discovered this forum. It is common to all the designs I try to synthesize with ISE.

[sushantm]

Verify your module description has a correct name?

Yes it is some what related to file name or something cannot locate by the tool cannot find try to do synthesis with default option.

Also it seems you are taking your own verilog code from other project in wich it is already synthesized?

[olufola]

I wrote the Verilog code myself and only simulated it with Modelsim. I'm using ISE for the synthesis just because a Virtex6 FPGA is the target device. There is no process named "Implementation Process" in ISE. Did you mean "Implement design"?

[olufola]

Verify your module description has a correct name?
The module giving the problem is named CyclicBench which does not violate any naming rules in Verilog. Maybe each module must go into a file with the same name or something?

[sushantm]

yes it is.

Also I'll suggest you to synthesize your code  and try to give ngc file instead of .v file.

And synhesize your project again.

[olufola]

All I have for now is the .v file. Any attempt to run any process on that file gives that errors even mere syntax checking. I thought ISE should generate the ngc file for me once the .v code is synthesized?