10-30-2011 09:03 PM
I am doing a timing (post synthesis and PAR) simulation with a design contains block memories.
I used approraite attribute in synthesis and PAR steps to reserve all design hierachies.
I need to initialize the memories with different code images for different tests,
I can see the hierachical reference name of memory like this:
but if I use the refenance name mentioned above, I got "Hierarchical name component lookup failed" in ncsim.
How can I initialize block memory in such situation ?
ISE Version 13.2
NCSIM version 10.20
11-02-2011 09:45 AM
I copied the name directly from NCSIM's design browser for a post-synthesis flattened design.
If I use a post-synthesis design keeps all design hierachy, I got a different reference name
but still could not recognized.
Maybe some kind of inconsistence between xilinx and ncsim software?
I filed a formal support ticket a few days ago and did not get any help yet.