Simulation and Verification

[tangqinghui]

I am doing a timing (post synthesis and PAR) simulation with a design contains block memories.

I used approraite attribute in synthesis and PAR steps to reserve all design hierachies.

I need to initialize the memories with different code images for different tests, 

I can see the hierachical reference name of memory like this:

fpga_top.u_mcu.u_sys.u_code_sram.@{\U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram }.genblk1.INT_RAMB_TDP.mem[2047:0][15:0] 

but if I use the refenance name mentioned above, I got "Hierarchical name component lookup failed" in ncsim.

How can I initialize block memory in such situation ?

ISE Version 13.2

NCSIM version 10.20

[graces]

How did you determine the hierarchical name?

The name seems incorrect as it contains @ {...

[tangqinghui]

I copied the name directly from NCSIM's design browser for a post-synthesis flattened design.

If I use a post-synthesis design keeps all design hierachy, I got a different reference name

 tbench.fpga_top.u_mcu.u_sys.u_code_sram.\U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.SIMPLE_PRIM36.ram.genblk1.INT_RAMB_TDP.mem[0][15:0]

but still could not recognized.

Maybe some kind of inconsistence between xilinx and ncsim software?

I filed a formal support ticket a few days ago and did not get any help yet.