02-01-2010 10:34 PM - edited 02-01-2010 10:41 PM
I am trying to run MIG simulation. The functional simulation works fine. when I run post place & route simulation, signal phy_init_done does not assert at all. I try to debug the MIG design and find the stage 1 calibration can not been done yet.
The root cause is the IODELAY of DQ does not work correctly. when the idelay_count vaule varies, there is no delay between input and output of the IODELAY component. I have checked SDF file and find this component has 0 propagation delay. I also check timing analysis of the component and it shows the correct value that is set. Are there any problem with simulation model of IODELAY? Could you check simulation. I try it with ISE 10.1 and ISE11.1
05-30-2011 06:28 PM
If you simulator is ncverilog, you can try below method:
the input delay for dq is always fixed as 0 when the delay_mode option of ncelab is set to path.
Please set the delay_mode to default and rerun the postsim.