Simulation and Verification

[wfjmueller]

running a test bench under ISE 11.3 ISim ends prematurely with

   INFO: Simulator is stopped.

No error message before. Simulation time (show time) is at 275ns, in fact just in the early initialization phase of the test bench. The same vhdl runs fine for example under 'ghdl'. So I  wonder under which conditions the "Simulator is stopped." informal message is generated. 

I'm not saving lots of signals in a vcd files, so AR #33429 does't seem to apply.

Any help or hint greatly appreciated.

Walter 

[evgenis1]

Hi Walter,

Check if "Simulation Run Time" in ISIM "Process Properties" is not set to 275ns. This setting seems to override your testbench. 

Hope that helps,

OutputLogic

[wfjmueller]

Hi,

thanks for the tip. I was a little imprecise: I've Webpack 11.3, used fuse to build an executable, started this isim executable without any options, and gave a 'run all' command. I've several other, self-checking test benches, and this procedure works well for them, the simulation runs till the clock is stopped at the end.

But to followup your hint I've also done a build and simulation start via the ISE gui. Same result, the simuation stops at 275 ns. I checked the process property 'Simulation Run Time', the ISE default seems to be 1000 ns, but the simulation stops at 275ns, setting it to a larger value doesn't help too.

I used 'isim ptrace on' and 'isim ltrace on' and got

275 ns "tb_rripdp.vhd":386
275 ns "tb_rripdp.vhd":387
.reset
275 ns "tb_rripdp.vhd":388
275 ns "tb_rripdp.vhd":389
INFO: Simulator is stopped.

and the associated code looks like

385        when ".reset" =>              -- .reset
386         write(oline, string'(".reset"));
387         writeline(output, oline);
388         RESET <= '1';
389         wait for clock_period;
390         RESET <= '0';

so it does a writeline, sets the signal, and never goes beyond the 'wait for clock_period'.

So I still wonder under which conditions the

   "Simulator is stopped."

informal message is generated.

Walter

Message Edited by wfjmueller on 2009-11-24 09:01 PM

[wfjmueller]

Hi all,

 I did a little more testing, in the end adding the definition of an otherwise unused signal before the definition of the signal RESET like

   signal USELESSSIGNAL : slbit := '0';
   signal RESET : slbit := '0';

made the test bench work, and produce the same results I get for example with ghdl.

So it seems that the vhdl compiler in ISim 11.3 is a still a little fragile, adding an unused signal shouldn't have such an effect. 

Walter 

[duthv]

Hi Walter,

You are correct. Adding an unused signal should have such an effect. Can you open a case with Xilinx Tech Support and send in the files?

http://www.xilinx.com/support/techsup/tappinfo.htm

We would like to take a closer look at the design.

Thanks

Duth

[wfjmueller]

Hi Duth,

I've submitted already a WebCase on Friday afer I found a second case where adding an unused signal definition made a test bench work.

It's case # 810466, all sources and a brief README are attached as tarball to the case.

Thanks for your help,

Walter

[lordali]

I have same issue. I don't know what vcd file is (i watched wiki too), but...

I use simple code for reading buttons from joystick on a kit. And simulator do the same.

Can somebody explain how to add that useless signal to get simulation working, pls? It's not working for me.