Simulation and Verification

[jays_xil_giga]

  I tried out ISE 14.1 and found that post-route simulation compile fails due to errors in the ISE generated  timesim.vhd file  for my code.  So at this point I cannot simulate the same design that has been working since earlier versions ISE 13. 

    I was wondering if anyone else has downloaded the new ISE 14.1 tool and has tried to generate a post-route simulation compile and got errors due to the timesim.vhd file?

First compile error I get is

ERROR:HDLCompiler:288 - "F:/xxxxx/netgen/par/xxxx_timesim.vhd" Line 10824: Cannot read from 'out' object ice ; use 'buffer' or 'inout'ERROR:HDLCompiler:854 –

"F:/xxxx/netgen/par/xxxx_timesim.vhd" Line 10778: Unit <structure> ignored due to previous errors.

For ISE 14.1 on line 10824 of ISE generated ___timesim.vhd

inc <= ice;

For ISE 13.4 generates

inc <= NlwRenamedSignal_ice;

ice <= NlwRenamedSignal_ice;

 I was hoping that xilinx got ISM fixed in 14.1 to display analog output like modlesim did. Oh well so much for Xilinx listening to end users needs.  

[scampbell]

Hello Jays...

I have seen this issue in 14.1 when there are unused ports where the VHDL based simulation file incorrectly tries to read from the ports. This is being investigated by the engineering team, but one potential workaround in the mean time is to use a verilog simulation file along with your VHDL testbench.

Also, the new Vivado simulator does in fact include an analog waveform viewer. Unfortunately, that could not be back-ported to the older ISim tool. I know that sometimes it does take a while for a suggestion to be implemented in the software tools, but we do take feedback very seriously, and always attempt to accomodate those suggestions in our tools.

OK, hope this helps ...

Scott