Simulation and Verification

[frozinite]

Hi,

I'm trying to simulate a [what I thought was a] pretty standard and simple VHDL project (a simple state machine with three outputs) and the simulator consistently freezes when I attempt to simulate.  The waveforms will show up and simulate correctly, however, I get the "busy" cursor and can't click anything.  After about 30 seconds, the simulator closes and puts me back into the text-editor windows.  When I try to re-open the simulator, it does the same thing.  This didn't used to happen, but I couldn't figure out what I changed before this started happening.  Any ideas?  Let me know what information you need.

Thanks

Edit: This is on Xilinx ISE Webpack 10.1 (Updated to latest version)

Edit2: Log file clip:

isimrun 500 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.

ERROR: Signal EXCEPTION_ACCESS_VIOLATION received

INFO:Simulator:30 - Simulator is stopped.
ERROR: Signal EXCEPTION_ACCESS_VIOLATION received

Message Edited by frozinite on 12-24-2008 01:32 AM

Message Edited by frozinite on 12-24-2008 01:36 AM

[duthv]

Hi,

Can you try this again? This time start by opening your process window and then see if you see a .exe file running such as designname_beh.exe, if there is, kill this process manually.

A lot of the times when you get a crash, this executable does not get cleaned up automatically and so you will keep seeing these crashes.

We will fix this in 11.1 to give a better message rather than crash.

Hope this helps

Duth

[frozinite]

I don't see a x_beh.exe running in the process.  When I start the simulation, it does come up on the process list, but only for a split second, and then closes immediately.  I've also tried restarting with no success.

[edv]

frozinite,

Try the following:

First, delete the "isim" folder by either using "Clean Up Project Files" from the Project menu, or manually deleting the "isim" folder in your project directory.

Second, try launching the simulation without a specified runtime.  It'd be interesting to learn whether the simulator fails to launch even before it simulates a few ns. To do this, right click on Simulate Behavioral Model, select Properties....  Uncheck "Run for Specified Time".  Click OK, and double-click Simulate Behavioral model.  If the simulator launches, then run for 1 us or so, using the run command: "run 1 us". 

If the error persists, consider opening a WebCase via http://www.xilinx.com/support/clearexpress/websupport.htm to have an Applications Engineer help you further with this issue.

[briandrummond]

I believe this message indicates the problem...

isimrun 500 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.

ERROR: Signal EXCEPTION_ACCESS_VIOLATION received

ACCESS VIOLATION (or signal SIGSEGV under Linux) means the ISE simulator has crashed;

so there's no surprise you can't see its executable running.

There are many ways to bring ISIM down with an  EXCEPTION_ACCESS_VIOLATION.

I recommend inserting lots of "Report" statements in your code until you can identify the specific VHDL

construct which is causing the problem. Then re-write your code to avoid it; but also create a testcase 

to demonstrate it and submit a Webcase to Xilinx.

A few of these ways to crash ISIM are documented in

http://www.xilinx.com/support/answers/30913.htm

But also:

(a) returning an access type (e.g. Line = access to string) from a function.

Pass it through an OUT mode parameter instead.

(b) Connecting to a Verilog component from VHDL std_logic ports.

Use intermediate signals instead of connecting ports directly; this is  tricky with INOUT ports!

(c) Switching between behavioral and post-route simulation without "Project Cleanup" and "Rerun All".

Updating from 10.1SP1 to 10.1SP3 fixes this one.

(d) Something to do with shared signals in packages (I haven't identified this one yet)

There may well be others too...