Simulation and Verification

[wilber1222]

Hi ,    

I have created a DDR2 Controller IP core based on "ug818_ddr2_mem_tutorial", but I created it by MIG v3.8  in Xilinx ISE 13.2 on Windows 7.

When I use ISim to run hardware co-sim , it report error listed below:        

ERROR: In process wrapperAHIL_INITIALIZE

Failed to open hardware co-simulation instance.

Could not locate the device "xc6slx16" at boundary scan position 1 on any JTAG cable.

INFO: Simulator is stopped.

If any of you here have faced this problem and know a solution, please let me know.

Thanks a lot!

Best  Regards.

[eilert]

Hi,

what board do you use?

Is it a Digilent Nexys3?

Check the JTAG chain with Impact to see the position of the FPGA in that chain.

Then change the settings for the HW-Cosim to the correct value, provided Impact was able to find a JTAG chain at all.

Have a nice simulation

  Eilert

[wilber1222]

Hi,

I do this simulation  based on the tutorial UG818, all of setting is same as the tutorial. In the document, that use Spartan®-6 FPGA SP601 Evaluation Kit.

Actually, I don't have the board at all. I just want to see the waveform of the tutorial.

Should I have the board to do the exercise or not?

Please help me, thans a lot.

Best Regards.

[eilert · Accepted solution]

Hi,

so if there's no hardware (FPGA board) connected to the simulator, how should a HW-cosimulation be possible?

Of course you need the board. Where should the values in the waveform come from.

Otherwise it would be a normal simulation, instead of a HW-Cosimulation.

On page 23 of UG818 you read:

"Before the simulation starts, ISim programs the FPGA with the bitstream file generated for hardware co-simulation."
How's that going to happen, if there's no FPGA (board)?

Have you understood the purpose of a HW-cosim at all?

Have a nice simulation

  Eilert