Simulation and Verification

[farthan]

Hi to everyone and thanks in advance for your help.

After having installed ISE 11.1 on a server (with Windows server 2003 as OS), I'm facing the following problem on Isim (lite version): after a period of simulation time (let's say 1e6ns), the clock signal doesn't get updated anymore and the console display the message "tracing limit is reached. Signal tracing will stop!".

Do you know how to fix it up?

Thanks a lot, if you need more information just ask

[pipowitsch]

Hi,

i have the same problem and i have spent a long time trying to solve it, without success. Did you manage to solve it?

thanks

[farthan]

Nope, not yet. I hope that some expert here will help us to find the clue

[kdeepak · Accepted solution]

Hello,

In 11.1, in order to stop ISim GUI from running out of memory, we put a limit on number of waveform transitions that can be saved in the waveform database file (the .wdb file). This limit is on total number of transitions. So, in order to see past the time point it stopped tracing for you, you can do following:

• Install 11.2 update. In 11.2, we reduced the memory requirement of waveform database by up to around 5X to 10X depending upon the signal types. So, you should be able to trace for a lot longer time.
• If you want to continue with 11.1 or if even after installing 11.2, you get hit by the limit, you can do following:
  • Trace only the signals you are interested in as opposed to tracing all the top level signals (You can delete the signals that are not important to be traced from your waveform configuration and restart simulation) 
  • Instead of tracing from time 0, shift the start time of tracing to a later point. For example, if you are interested in seeing results at around 1000 us, then you can run simulation up to 900 us with no signal being traced (you can disable tracing by simply deleting the signals from waveform configuration e.g. By selecting signals in waveform configuration window and then hitting the delete key) and then add the signals back to waveform configuration at 900 us and then run for 100 us. You will see that only 900 us to 1000 us duration of waveform is shown. Then you can shift the time window as desired by restarting the simulation and choosing off and on time of tracing as per your need. To do it in command line you can run following Tcl command as an example: ntrace stop; run 900 us; wave add /; run 100 us;

I hope that helps.

Kumar 

Message Edited by kdeepak on 08-18-2009 02:39 PM

[pipowitsch]

thank you for the help. does the ISIM Lite version (meaning if i only have a webpack license) have a lower tracing limit then the full version?

[kdeepak]

Lite and Full version has the same limit on waveform tracing.

We will improve the message in 12.1 to say something like this:

"A limit on number of transitions that can be stored in waveform database (.wdb) file has been reached and waveform tracing has been stopped. If you want to view waveform past this time point, try tracing fewer signals or trace only for the time window of your interest as opposed to tracing starting from time 0. You can trace only for the time widnow of your interest by running 'restart; ntrace stop; run <time when tracing is not done>; wave add /sig1 /sig2 .. ; run <time when tracing is done>' "

Thanks for reporting the issue!

[jrsopha]

I am using ISE 11.3 and the full version of ISIM.  In an attempt to duplicate my original simulation where I did not see the "tracking limit is reached" warning, I deleted all *.wdb and *.wcfg files.  Unfortunately this did not work.  Any and all suggestions are welcome.

[duthv]

Hello,

The limit is going to be there, until we make some changes to the simulator to fix the limit. This is there to ensure that you dont have a memory crash. We are working on reducing the memory foot print in the future.

In the interim, please try to trace lesser signals than what you are tracing right now and you should see the problem goes away.

Also can you try 12.1? The memory footprint is slightly reduced in that version. Additionally feel free to open a case with tech support, if you need assistance on tracing less signals.

http://www.xilinx.com/support/techsup/tappinfo.htm

Thanks

Duth

[bkmosch]

I updated ISE from 11.4 to 12.1 and opened a previous project in 12.1 which then updated the project to a 12.1 format.  The test benches no longer ran correctly and was giving nonsense waveforms and errors.  I decided to copy one .vhd file with its test bench to a new folder, created a new project with those 2 files only, and the test bench showed good waveforms when I ran it for 300 ms.  I then copied only the test bench (which I made minor modifications to) back to the original project files.  Then, to get rid of what I'm assuming was a corrupted project, I deleted all files & folders except for my .vhd and .ucf files.  I created a new project, added those files, and tried simulating that same test bench that worked fine last week.  Now I immediately get the "tracing limit" error with no transitions showing at all on the wave display (I'm obviously not hitting any valid limit).  Anyone have any clue what is going on?  I'm just about to the point of reinstalling 11.4 again so I can use ModelSim again (since a bug with 12.1 prevents this).  But...

I'm going to try one more time recreating a new project, but this time in a different folder with a different project name than it originally had.  I'm suspecting there is some lingering reference somewhere to the previous (corrupted) project.

[bkmosch]

I fixed my corrupted project.  Everything stopped acting wierd after connecting a few signals to unconnected ports and recreating test benches for each of the components used at the top level (the test benches had outdated port names, etc.).  Oh, and I noticed that in the simulation view there was a file appearing at the same level as the other test benches, but it wasn't a test bench.  It was a file not being used anyway, so I deleted it out of the project.  After that (and recreating test benches) everything seems fine.  I no longer get that "tracing limit" error.  Wierd.

I believe that Xilins should add more project file cross checking to ISE.  I've corrupted projects before by doing other things which shouldn't have caused problems, such as adding and deleting libraries and library files.  I've learned that, once a project starts acting wierd, the quickest way to see something wrong is to select the top level file and choose Synthesize >> View RTL Schematic.  Drill down through the blocks to make sure everything is connected correctly.  When my projects were corrupted, the connections in this diagram were obviously wrong (didn't match the VHDL code).