Simulation and Verification

[joryte]

Hello,

I'm using ISE 13.2 to manage a project that has an embedded processor EDK project.  The Microblaze has a DDR3 peripheral and I am trying to simulate the system.  My language of choice is VHDL.  In the Simulation view of ISE I select the EDK object and select "Generate HDL Test Bench (XPS)" after enabling external memory simulation in the source properties.  The testbench is created fine and instantiates the embedded processor and a handful of ddr3 modules.  I understand that I need a memory model, but one isn't generated for me automatically.  I can however find ddr3_model.v (and its associated ddr3_model_parameters.vh) in the __xps/DDR3_SDRAM/ folder.  However, when I rename it to ddr3.v and place it in the edk project's root directory I get compilation errors (typically array range direction mismatches).  Is the process of generating the HDL test bench through XPS supposed to also generate a compatible DDR3 memory model?  Where am I supposed to find a correct model?

Generating simulator compile script ...
WARNING:EDK:4226 - Unable to locate the external memory model file ddr3.v/vhd,
   which is required to build library work. Make sure to copy this file into
   project directory before elaboration.

ERROR:HDLCompiler:1134 - "Unknown" Line 0: Cannot open verilog file ....../ddr3.v


Thanks,

JoRyTe

[joryte · Accepted solution]

I was able to solve the issue by using the ddr3_model.v and ddr3_model_parameters.vh in the __xps folder.  Of course, I had to change ddr3_model filename and module name to ddr3 and copy both files into the EDK project's root directory.  However, I still had lots of errors.  Looking at the isim_files.prj file in the user_design folder of a MIG project generated from CoreGen for the same memory I was able to discover the necessary user defines that are missing, for some reason, from my ISE-auto-generated project and compile script.  I opened the ddr3.v file and added the following lines before the include of ddr3_model_parameters.v, even though they don't exactly match the memory chosen in MIG (presumably, the memory model is the same under these parameters):

`define x1Gb

`define sg187E

`define x16

After this, all errors were resolved and compilation for simulation succeeded.

Thanks,

JoRyTe

[matthewkim.lockie]

Hi Joryte,

I am trying DDR3 EDK system simulation but the DDR3 memory simulation model has some problems to do the system simulation.

Have you tried EDK system simulation using DDR3?

If you have, I would like to get some tips on this.

This is my previous post.

http://forums.xilinx.com/t5/EDK-and-Platform-Studio/SP605-EDK-System-Simulation-DDR3-memory-initiali...

Thanks and regards,

Matthew

[joryte]

Hi Matthew,

I have done a few simulations of EDK projects with DDR3.  I have never had to perform initializations or otherwise modify the testbench to get them to work.  The only modifications I had to make were to the memory model, as identified in my original post.  These mods were required to get the system to compile.  Once the system compiled, simulation proceeded normally.  I'm not sure what the error is you are running into, as my limited experience has not produced any similar results.

Good Luck,

JoRyTe

[matthewkim.lockie]

Hi JoRyTe,

Thank you very much for your response.

I am currently testing EDK system simulation.

I am initializing the DDR3 memory simulation model on my verilog testbench.

But the simulation model is not working well for the EDK system simulation.

I have checked the MCB simulation after generation the MCB example desing using Coregen and the model is working well for the MCB example design.

They have different scheme. In case of MCB example design, they are writing the data first and read the data.

But in case of EDK system simulation, we initialize the memory on the verilog testbench.

When I tried the memory on my System simulation. The output was just "XXXX".

Finally, I would like to know you have test the EDK system simulation on your side using DDR3 memory simulation model or you know any example design on this.

Thanks again.

Matthew