Hi people,
I having a quite interesting problem with my current proyect. Let me give you some context :
I'm tring to implement a kalman filter in a Spartan 6 (LX150T) using ISE 12.4 and Isim for simulations.
My design derived to a system conformed like this:
The module Bierman is a combinational block :
--------------------------------------------------
--Libraries:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM; -- Used to simulate when using componetes of the library
use UNISIM.VComponents.all;
use work.parameters.ALL; -- Our packages
use work.system_def.ALL;
use work.Fixed_Point_pkg.ALL;
--------------------------------------------------
entity Bierman is
Port ( Z : in WORD;
Xp : in WORDV_n;
UPp : in WORDV_UT;
DPp : in WORDV_n;
Xpo : out WORDV_n;
UPpo : out WORDV_UT;
DPpo : out WORDV_n);
end Bierman;
architecture Mixed of Bierman is
begin
scalar_bierman : process(Z, Xp, UPp, DPp) is
variable dz, alpha, gamma, beta, lambda, R_int, s_aux, s_aux1: S_WORD; -- Internal aux variable.
variable X, H_int, V, D, b : S_WORDV_n; -- Internal aux vectors.
variable U : S_WORDV_UT; -- Internal aux vector to store the unit upepr triangular matrix U.
variable i : counter_n ;-- used in the variable loops (while)
variable index_aux : counter_UT ; -- used as index of UT vector
variable index : counter_l;
begin
-----------load the input signals-------------------------
for k in 1 to n loop -- load and converts Xp to a internal variable
X(k) := signed(Xp(k));
end loop;
for k in 1 to ((n*n-n)/2) loop -- load and converts UPp to a internal variable
U(k) := signed(UPp(k));
end loop;
for k in 1 to n loop -- load and converts DPp to a internal variable
D(k) := signed(DPp(k));
end loop;
for k in 1 to n loop -- load and converts H to a internal variable
H_int(k) := signed(H0(1,k));
end loop;
R_int := signed(R0(1));
dz := signed(Z);
-------------starts the Bierman algorithm--------------------------
for j in 1 to n loop
dz := fp_add(dz,fp_comp(resize_x2(H_int(j)*X(j))));-- computes Z-H*X
V(j) := H_int(j);
i := 1;
while true loop -- equivalent to: for in 1 to (j-1) (iterates j-1 times)
if i = j then
exit;
end if;
index_aux := j-n+(i*(2*n-i-1))/2 ; -- to find the element Uij inside the U vector
V(j) := fp_add(V(j),resize_x2(U(index_aux)*H_int(i)));-- computes V=U'*H'
i := i+1 ;
end loop;
end loop;
for k in 1 to n loop
b(k) := resize_x2(D(k)*V(k)) ; -- computes the b factor in the Grewall's Bierman matlab algorithm (called the unescaled kalman gain)
end loop;
alpha := R_int ;
gamma := fp_reciprocal(alpha);
for j in 1 to n loop
beta := alpha;
alpha:= fp_add(alpha,resize_x2(V(j)*b(j))) ;
lambda:=fp_comp(resize_x2(V(j)*gamma)); --value s_aux complemanted
gamma := fp_reciprocal(alpha);
D(j):= resize_x2(beta*resize_x2(gamma*D(j)));
i := 1;
while true loop -- equivalent to: for in 1 to (j-1) (iterates j-1 times)
if i = j then
exit;
end if;
index_aux := j-n+(i*(2*n-i-1))/2 ; -- to find the element Uij inside the U vector
beta := U(index_aux);
U(index_aux):= fp_add(beta,resize_x2(b(i)*lambda));
b(i) := fp_add(b(i),resize_x2(b(j)*beta));
i := i+1 ;
end loop;
end loop;
for k in 1 to n loop
X(k):= fp_add(X(k),resize_x2(resize_x2(gamma*dz)*b(k)));
end loop;
for k in 1 to n loop -- assign the internal X to the output signal Xpo
Xpo(k) <= std_logic_vector(X(k)) ;
end loop;
for k in 1 to ((n*n-n)/2) loop -- assign the internal U to the output signal UPpo
UPpo(k) <= std_logic_vector(U(k)) ;
end loop;
for k in 1 to n loop -- assign the internal D to the output signal DPpo
DPpo(k) <= std_logic_vector(D(k)) ;
end loop;
end process scalar_bierman;
end Mixed;
When I sintethize Bierman block as top module it uses 11 Embedded DSP48 modules.
The Thornton Block is also a combinational block:
--------------------------------------------------
--Libraries:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM; -- Used to simulate when using componetes of the library
use UNISIM.VComponents.all;
use work.parameters.ALL; -- Our packages
use work.system_def.ALL;
use work.Fixed_Point_pkg.ALL;
--------------------------------------------------
entity Thornton is
Port ( Xpo : in WORDV_n;
UPpo : in WORDV_UT;
DPpo : in WORDV_n;
Xp : out WORDV_n;
UPp : out WORDV_UT;
DPp : out WORDV_n);
end Thornton;
architecture Behavioral of Thornton is
begin
scalar_thornton: process (Xpo,UPpo, DPpo) is
variable sigma, s_aux : S_WORD; -- Internal aux variable.
variable X, Xout, V, D, Dout, b, uc_int : S_WORDV_n; -- Internal aux vectors.
variable U, Uout : S_WORDV_UT; -- Internal aux vector to store the unit upepr triangular matrix U.
variable Phi_int, PhiU : S_WORDM_nxn;-- Internal aux nxn matrices
variable DQ_int : S_WORDV_p;-- Internal aux pxp matrices
variable G_int : S_WORDM_nxp;-- Internal aux pxp matrices
variable j,r : counter_n ;-- used in the variable loops (while)
variable index_aux, index_aux1 : counter_UT ; -- used as index of UT vector
begin
-----------load the input signals-------------------------
for k in 1 to n loop -- load and converts Xp to a internal variable
X(k) := signed(Xpo(k));
end loop;
for k in 1 to ((n*n-n)/2) loop -- load and converts UPp to a internal variable
U(k) := signed(UPpo(k));
end loop;
for k in 1 to n loop -- load and converts DPp to a internal variable
D(k) := signed(DPpo(k));
end loop;
for i in 1 to n loop
for j in 1 to n loop -- load and converts Phi to a internal variable
Phi_int(i,j) := Phi0(i,j);
end loop;
end loop;
for i in 1 to p loop -- load and converts DQ to a internal variable
DQ_int(i) := DQ0(i);
end loop;
for i in 1 to n loop -- load and converts G to a internal variable
for j in 1 to p loop
G_int(i,j) := G0(i,j);
end loop;
end loop;
for k in 1 to n loop -- load and converts c to a internal variable
uc_int(k) := uc(k);
end loop;
-------------starts the Thornton algorithm--------------------------
PhiU := NULL_S_WORDM_nxn ;
for i in 1 to n loop --PhiU = Phi*U(:,:,k)
for j in 1 to n loop
r:=1;
while true loop -- equivalent to: for r=1 to (j-1) but vhdl implementable
if r = j then
exit;
end if;
index_aux := j-n+(r*(2*n-r-1))/2;-- to find the element Uij
PhiU(i,j):= fp_add(PhiU(i,j),resize_x2(Phi_int(i,r)*U(index_au
r:=r+1;
end loop;
PhiU(i,j):= fp_add(PhiU(i,j),Phi_int(i,j));
end loop;
end loop;
for i in n downto 1 loop
sigma := null_S_WORD;
for j in 1 to n loop
sigma := fp_add(sigma, resize_x2(PhiU(i,j)*resize_x2(PhiU(i,j)*D(j)))) ;
if (j < p+1) then
sigma := fp_add(sigma,resize_x2(G_int(i,j)*resize_x2(G_int(
end if;
end loop;
Dout(i) := sigma;
j:=1;
while true loop -- equivalent to: for j=1 to (i-1) but vhdl implementable
if j = i then
exit;
end if;
sigma := null_S_WORD;
for s in 1 to n loop
sigma := fp_add(sigma,resize_x2(PhiU(i,s)*resize_x2(D(s)*Ph
end loop;
for s in 1 to p loop
sigma := fp_add(sigma, resize_x2(G_int(i,s)*resize_x2(DQ_int(s)*G_int(j,s
end loop;
index_aux := i-n+(j*(2*n-j-1))/2 ; -- to find the element Uji inside the U vector
Uout(index_aux) := resize_x2(fp_reciprocal(Dout(i))*sigma);
for s in 1 to n loop
PhiU(j,s) := fp_add(PhiU(j,s),fp_comp(resize_x2(Uout(index_aux)
end loop;
for s in 1 to p loop
G_int(j,s) := fp_add(G_int(j,s),fp_comp(resize_x2(Uout(index_aux
end loop;
j := j+1;
end loop;
end loop;
--State estimation temporal update
Xout := NULL_S_WORDV_n;
for i in 1 to n loop
for r in 1 to n loop
Xout(i):= fp_add(Xout(i),resize_x2(Phi_int(i,r)*X(r)));
end loop;
Xout(i):= fp_add(Xout(i),uc_int(i));
end loop;
for k in 1 to n loop -- assign the internal X to the output signal Xpo
Xp(k) <= std_logic_vector(Xout(k)) ;
end loop;
for k in 1 to ((n*n-n)/2) loop -- assign the internal U to the output signal UPpo
UPp(k) <= std_logic_vector(Uout(k)) ;
end loop;
for k in 1 to n loop -- assign the internal D to the output signal DPpo
DPp(k) <= std_logic_vector(Dout(k)) ;
end loop;
end process scalar_thornton;
end Behavioral;
When I sintethize Thornton block as top module it uses 16 Embedded DSP48 modules as non registered multipliers
The data path module is basically a set of FF to feedback the results from one block to the other:
--------------------------------------------------
--Libraries:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library UNISIM; -- Used to simulate when using componetes of the library
use UNISIM.VComponents.all;
use work.parameters.ALL; -- Our packages
use work.system_def.ALL;
--------------------------------------------------
entity Data_path_controller is
Port ( Xin_B : in WORDV_n;
Xin_T : in WORDV_n;
UPin_B : in WORDV_UT;
UPin_T : in WORDV_UT;
DPin_B : in WORDV_n;
DPin_T : in WORDV_n;
CE : in STD_LOGIC;
clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Xout_B : out WORDV_n;
Xout_T : out WORDV_n;
Xout_ext : out WORDV_n_AUX;
UPout_B : out WORDV_UT;
UPout_T : out WORDV_UT;
DPout_B : out WORDV_n;
DPout_T : out WORDV_n);
end Data_path_controller;
architecture Behavioral of Data_path_controller is
begin
secuential: process (clk,CE,Reset) is
variable state: counter_lp1 ;
variable X_int , DP_int : WORDV_n ;
variable UP_int : WORDV_UT ;
begin
If Reset='1' then
state := 1 ;
for k in 1 to n loop
Xout_B(k) <= std_logic_vector (X0(k)) ; -- Initial conditions
end loop;
for k in 1 to n loop
DPout_B(k) <= std_logic_vector (DP0(k));
end loop;
for k in 1 to ((n*n-n)/2) loop
UPout_B(k) <= std_logic_vector (UP0(k));
end loop;
elsif clk'event and clk='1' and CE='1' then
case state is
when 0 => -- Bierman Operation (1 time)
X_int := Xin_T;
DP_int := DPin_T;
UP_int := UPin_T;
for i in 1 to n loop -- Load the output
for j in 0 to WORD_LENGTH-1 loop
Xout_ext(i,j) <= X_int(i)(j) ;
end loop;
end loop;
Xout_B <= X_int ;
DPout_B <= DP_int;
UPout_B <= UP_int;
state := state + 1 ;
when l => -- Thornton Operation (1 time)
X_int := Xin_B;
DP_int := DPin_B;
UP_int := UPin_B;
for i in 1 to n loop -- Load the output
for j in 0 to WORD_LENGTH-1 loop
Xout_ext(i,j) <= X_int(i)(j) ;
end loop;
end loop;
Xout_T <= X_int ;
DPout_T <= DP_int;
UPout_T <= UP_int;
state := 0;
end case;
end if;
end process secuential;
end Behavioral;
If I perform post-route simulations of each block alone, everything works great.
So the code seems to have no problems at a functional level.
When I sintethize the whole system ( the 3 modules all together) I get no warnings, and everything goes ok.
The behavioral simulation of this and It works well to.
The PROBLEM arises when I perform a post-synthesis simulation of the whole system. Here the results are not the same compared to those of the behavioral simulation. The values at the output differ.
After the "generate post-sunthesys simulation model" I get one warning:
WARNING:NetListWriters:303 - Unable to preserve the ordering for port bus E_X on
block KF_BT using the data E_X<2><17:0>.
I've spend plenty of time on debugin this but I haven't been able to find the error. From these tests some clues have arose:
-This is not a timing problem: I doesn't work at a post-synthesis level and I've also tried with very low clk freq
-The combinational blocks just respond in a diferent way (for the same input) in post-synthesis simulationwhen I test them alone and all together.
-My bets go for the synthesis of the DSP48. I haven't instanate them, I just used * and let XST work. I think that maybe the synthesis of * in the combinational modules is not the same when the modules are synthetized alone to when they are sinthetized with the FF of the Data_path module.
- Remember that I am using the DSP48 in a non-registered configuration, so no clk. I think that, XST doesn't shyntetize properly the * when I include the clk ( of the FF).
- I've already try with the keep hirerchy option
- I really don't know the efects of the only Warning I've got
- If I synthetize the whole proyect with the option dsp_use_ratio = 0% it works great !!!!!!
- If I synthetize the whole proyect with the option use_dsp = auto_max (only for spartan 6) it works great to !!!!!!
I'm quite stucked with this problem, any idea will be wellcome !
Thanks
PD: Sorry for the bad English
