Simulation and Verification

[sraza]

hello all!

While doing post map simulation, I got the following warning

WARNING: at 5910840 ps: Timing violation in /tb_meanSubtrction/uut/\B1/Mram_mem_blk / $setuphold<setup>( DIADI:5910724 ps, CLKARDCLK:5910840 ps,200 ps,337 ps)

For as far as I investigate looking at the figure, I got the hold time violation, i.e. at data lines the data does not remain for long enough time to be sampled. How to resolve this issue. Since my output is comming from a divider (i.e. uncontrollable by me) and now I have to store it in memory. So How can I remove this warning since this will affect my final desgin.

Note that the ouput that I am storing in memory is coming from a separate block uncomntrollabe by me(at least what I think....!) See the diagram if one can understand... I cannot find any better way to explain....: (

Best Reagrds,

Shan

[austin]

Shan,

The data source must be synchronous (driven by the same clock), so that you can control how you receive the data by phase shifting the clock to your registers through the use of the DCM/PLL/MMCM (whatever chip you have, has a means to phase shift the clock).

Once you have registered the count in the phase-shifted clock domain, you can then re-register it to the original clock domain, or  continue to use the phase-shifted clock for the rest of the design.

Lastly, you could use the phase shifted clock to drive the original "black-box" counter to shift the data so it does not violate the hold time.

Rather than try to fiddle with the data (which you can not do, and is not a good thing to do anyway), shift the phase of the clock.