Simulation and Verification

[sridar]

Hi all,

Simulating my design in modelsim XE III starter shows the following warning

# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.132 ns; Observed := 0.08 ns; At : 2.952 ns
#    Time: 2952 ps  Iteration: 3  Instance: /tb_mydes/uut/a5_sreg1_0_brb2
# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.132 ns; Observed := 0.127 ns; At : 2.991 ns
#    Time: 2991 ps  Iteration: 3  Instance: /tb_mydes/uut/a5_sreg1_2.

 How exactly I can find the solution for this. I am not violating the timing given by xilinx tool. following is the timing details given by xilinx.

   Minimum period: 15.954ns (Maximum Frequency: 62.680MHz)
   Minimum input arrival time before clock: 3.319ns
   Maximum output required time after clock: 4.283ns
   Maximum combinational path delay: No path found

And my test bench timing is default as below

Clock high time : 100 ns

Clock low time : 100 ns

Input setup time : 15 ns

Output Valid Delay : 15 ns

Offset :  100 ns.

Message Edited by sridar on 11-03-2009 12:28 AM

[gszakacs]

Since your clock is running much slower than the reported max frequency, I suspect that

your input timing is not correct in the testbench.  Make sure you are meeting the hold time

required.  You can look at the datasheet report from the post P&R static timing to see

requirements at each pin.  Realise that a hold time violation on an external pin can show

up as a setup time violation in timing simulation.  Essentially the delay on the clock net is

modeled as the maximum delay from timing analysis.  If the data input doesn't meet the

required hold time, it beats the clock to the internal flip-flop by some amount that is

less that the setup time for the flop.

HTH,

Gabor

[surajpaul]

I am too getting smilar messages indicating violation of SETUP time of FFs while simulating the post route model in modelsim.

My testbench input clock frequency is 40 Mhz while xilinx post-route report shows the maximum freq. to be 53Mhz. Static timing analysis after PAR, shows no setup and holdtime error. Yet i am getting the SETUP violation on FFs during post route simulation.

The same test bench frequency gives correct output and no warnings/timing error till post-translate simulation. Any suggestion for this kind of behaviour?

PS: I am new to post PAR simulaiton. Any guidance or suggestion would help me explore the techniques.

[gszakacs]

I see at least three possibilities

1. Your inputs from the test bench don't meet the setup/hold time reported in the datasheet section of the post P&R timing report.
2. The flip-flops getting the SETUP errors are not covered by timing constraints.
3. The flip-flops getting the SETUP errors are at a clock domain crossing (often inside a FIFO) and the SETUP time should be ignored.

-- Gabor

[surajpaul]

Thanks you for ur feedback. Possibility 1. explained the problem i am facing. If i change my testbench thn the errors do not pop up during PAR sim.

Then in actual scenario after programminging the FPGA, how should i ensure that the inputs coming to FPGA dont  violate SETUP/HOLD time specified in datasheet section of PAR report? Do i need to modify the constraint in my design? Is this right approach. Kindly reply.

[gszakacs]

Then in actual scenario after programminging the FPGA, how should i ensure that the inputs coming to FPGA dont  violate SETUP/HOLD time specified in datasheet section of PAR report? Do i need to modify the constraint in my design? Is this right approach. Kindly reply.

First you need to know how much setup and hold time you really have in the hardware.  Normally

you would compute this from the data sheet values of the components driving the pins of the

FPGA, and the system level clock timing.

Then you need to constrain your design so that it meets the required timing.  For synchronous

inputs you need an OFFSET IN BEFORE type of constraint.

As an example, suppose you have a clock pin CLK_50 and a data pin DATA_IN.  The data on DATA_IN

is valid from 2.5ns before the clock (setup = 2.5ns) until 1.5ns after the clock (hold = 1.5ns).  Then your

constraint might be:

NET "CLK_50" TNM_NET = "CLK_50";
NET "DATA_IN" TNM = "input_data";

TIMEGRP "input_data" OFFSET = IN 2.5 ns VALID 4 ns BEFORE "CLK_50";

The VALID part needs to be the time the signal is valid and equals setup + hold or 4 ns in this example.

HTH,

Gabor

[rcingham]

Some very good information on timing constraints at
http://forums.xilinx.com/t5/PLD-Blog/Timing-Constraints-Part-1-of-5/ba-p/57594
and the rest of the series...