Simulation and Verification

[alexium]

Good time of day!

I decided to put aside the post-PAR model for a while, and try post-sinthesys.

"Check syntax" gives me an error: "Formal port/generic <\ADDRA{13}\> is not declared in <ramb16bwe>". And the second (and last) error is: "Formal <addra> has no actual or default value.". I don't understand how can those 2 errors combine at all...

I tried reading Spartan-3A FPGA User Guide, but seems like RAMB16BWE is not intended for manual instantiation, so there is no detailed specification of it's ports and generics.

Any ideas?

Thanks in advance.

P.S. My BRAM is VHDL source code, not a core.

[eteam00]

"Check syntax" gives me an error: "Formal port/generic <\ADDRA{13}\> is not declared in <ramb16bwe>". And the second (and last) error is: "Formal <addra> has no actual or default value."

Sounds like you have a problem in the code which generates ADDRA.

You should post your code for the module which contains the RAMB16BWE and the code which generates ADDRA.

I don't understand how can those 2 errors combine at all...

The both relate to the generation of ADDRA.

I tried reading Spartan-3A FPGA User Guide, but seems like RAMB16BWE is not intended for manual instantiation,

It most certainly is intended for manual instantiation.

so there is no detailed specification of it's ports and generics.

This is from the language templates (in ISE, EDIT > Language Templates).

Then VHDL > Device Primitive Instantiation > Spartan-3A > RAM/ROM > Block RAM > 16k...(RAMB16BWE)

   -- RAMB16BWE: 16k+2k Parity Paramatizable, byte-wide enable BlockRAM
   --            Spartan-3A
   -- Xilinx HDL Language Template, version 12.4

   RAMB16BWE_inst : RAMB16BWE
   generic map (
      DATA_WIDTH_A => 0, -- Valid values are 1, 2, 3, 4, 8, 18, or 36
      DATA_WIDTH_B => 0, -- Valid values are 1, 2, 3, 4, 8, 18, or 36
      INIT_A => X"000000000", --  Initial values on A output port
      INIT_B => X"000000000", --  Initial values on B output port
      SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY", 
                                    -- "GENERATE_X_ONLY" or "NONE" 
      SRVAL_A => X"000000000", --  Port A output value upon SSR assertion
      SRVAL_B => X"000000000", --  Port B output value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      -- The following INIT_xx declarations specify the initial
-- < 73 lines of init code deleted  -- Bob Elkind >
   port map (
      DOA => DOA,      -- 32-bit A port Data Output
      DOB => DOB,      -- 32-bit B port Data Output
      DOPA => DOPA,    -- 4-bit  A port Parity Output
      DOPB => DOPB,    -- 4-bit  B port Parity Output
      ADDRA => ADDRA,  -- 14-bit A port Address Input
      ADDRB => ADDRB,  -- 14-bit B port Address Input
      CLKA => CLKA,    -- Port A Clock
      CLKB => CLKB,    -- Port B Clock
      DIA => DIA,      -- 32-bit A port Data Input
      DIB => DIB,      -- 32-bit B port Data Input
      DIPA => DIPA,    -- 4-bit  A port parity Input
      DIPB => DIPB,    -- 4-bit  B port parity Input
      ENA => ENA,      -- 1-bit  A port Enable Input
      ENB => ENB,      -- 1-bit  B port Enable Input
      SSRA => SSRA,    -- 1-bit  A port Synchronous Set/Reset Input
      SSRB => SSRB,    -- 1-bit  B port Synchronous Set/Reset Input
      WEA => WEA,      -- 4-bit  A port Write Enable Input
      WEB => WEB       -- 4-bit  B port Write Enable Input
   );

-- Bob Elkind

[alexium]

That's what happens when you look through the manual instead of actually reading it. I missed the part about language template. Thank you.

The problem is: my RTL code is OK. It simulates and it works (in a way) in hardware. And I can't make heads or tails out of post-sinthesys model code (and I don't think I'm even supposed to).

By saying I should post my code for the module which contains the RAMB16BWE and the code which generates ADDRA, do you mean original RTL code?

[eteam00]

What tool generated the error messages?  What code did you "feed" to that tool?

-- Bob Elkind

[alexium]

HDLCompiler generated the message. The code I "fed" is a primitive testbench with UUT being post-sinthesys model (7400 lines of code).

[eteam00]

HDLCompiler generated the message. The code I "fed" is a primitive testbench with UUT being post-sinthesys model (7400 lines of code).

So you aren't using ISE/XST for synthesis.  Does your code synth, place, & route OK with ISE?  If so, then you seem to have a problem specifically between your code and HDLCompiler ?

Sorry, I'm not familiar with HDLCompiler.

Did you take my advice on the beer therapy?

-- Bob Elkind

[alexium]

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eteam00 wrote:

HDLCompiler generated the message. The code I "fed" is a primitive testbench with UUT being post-sinthesys model (7400 lines of code).

So you aren't using ISE/XST for synthesis.  Does your code synth, place, & route OK with ISE?  If so, then you seem to have a problem specifically between your code and HDLCompiler ?

Sorry, I'm not familiar with HDLCompiler.

Did you take my advice on the beer therapy?

-- Bob Elkind

---

I'm sorry,  my description of the situation wasn't clear. I do use XST for sinthesys. Everything sinthesyses, places, routes and even works in HW (with problems, as you may remember, but that's not the point here). I generated post-sinth model with XST. I then instanciated this model in my testbench, switched into "Simulation" view and performed "check  syntax" on a TB. That's where HDLCompiler runs and gives me those errors. My guess is HDLCompiler is a tool that is used by both XST and Isim as a first stage of HDL files processing. It is the tool that shows you syntax errors, and is used when you click "Check syntax".

As for your advice about beer therapy - I took it in my own way (I don't drink alcohol, but I relaxed drinking tea and watching my favourite TV series). I also took good sleep, but I can't feel any improvements in my understanding of the problem I'm facing. However, I'm feeling rational, mentally stable and able to reason adequately.

[eteam00]

I then instanciated this model in my testbench, switched into "Simulation" view and performed "check  syntax" on a TB. That's where HDLCompiler runs and gives me those errors.

That certainly helps narrow down the problem a bit, and the error messages seem quite specific.

However, I'm feeling rational, mentally stable and able to reason adequately.

You're doing better than most of us!

-- Bob Elkind

[alexium]

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eteam00 wrote:

That certainly helps narrow down the problem a bit, and the error messages seem quite specific. 

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Yes it is. But since my original RTL code is OK, and it's next to impossible to undersatnd something in those 7000 lines of post-sinthesys code, I have no idea how to fix the problem.

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eteam00 wrote:

You're doing better than most of us!

---

No, I'm just feeling better, there's a major difference between feeling and doing : )