Simulation and Verification

[hithesh]

Trying to convert std_logic vector to signed data type, but I keep getting - "no feasible entry for subprogram conv_signed"

I have declared all the libraries -

USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all; 

Conv and signal declaration in architecture-

SIGNAL ys: signed(7 downto 0);

ys<=conv_signed(sum,8);

Any help?

[bassman59]

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hithesh wrote:

Trying to convert std_logic vector to signed data type, but I keep getting - "no feasible entry for subprogram conv_signed"

I have declared all the libraries -

USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all; 

Conv and signal declaration in architecture-

SIGNAL ys: signed(7 downto 0);

ys<=conv_signed(sum,8);

Any help?

---

yeah -- DO NOT use std_logic_arith and its compadres std_logic_unsigned and std_logic_signed.

Use numeric_std instead.

-a

[hithesh]

Bassman, thanks for the response.

But I also tried numeric_std.all library. I get the following error -

(vcom 1136)  unknown identifier conv_signed.

 The usage of numeric_std - is it something new, bcoz most of the books dont mention it at all.

[briandrummond]

Something new? It's at least 15 years old!

"conv_signed" is a pretty bad name for a function anyway ... does it convert FROM signed or TO signed?

Which is why the equivalent function in nomeric_std is called... "to_signed". Use that instead.

[hithesh]

I am trying to convert a std_logic_vector to a signed type.

Conv_signed should convert, std_logic_vector, unsigned, signed, and integer to signed datatype.

Apparently it is not working. 

I tried to_signed , got an error - "No feasible entries for subprogram to_signed"

[briandrummond · Accepted solution]

oops, sorry:

to_signed would convert from integer types to signed.

std_logic and signed are compatible subtypes; you only need a cast, not a conversion.

my_signed <= signed(my_slv);

my_other_slv <= std_logic_vector(my_signed);

Of course the signals need to be the same size.

[bassman59]

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hithesh wrote:

I am trying to convert a std_logic_vector to a signed type.

Conv_signed should convert, std_logic_vector, unsigned, signed, and integer to signed datatype.

Apparently it is not working. 

I tried to_signed , got an error - "No feasible entries for subprogram to_signed"

---

 

See VHDL Math Tricks of the Trade.

 

[hithesh]

Thanks guys. It worked.

But now, I don't see the point of having signed type. 

Signed subration and unsigned subration give the same result, except that the MSB of singed indicates sign.

(If I consider 3-5 in binary, unsigned gives  110, signed results in 1110. Both are the same : -2). 

Why have 2 types? 

[bassman59]

---

hithesh wrote:

Thanks guys. It worked.

But now, I don't see the point of having signed type. 

Signed subration and unsigned subration give the same result, except that the MSB of singed indicates sign.

(If I consider 3-5 in binary, unsigned gives  110, signed results in 1110. Both are the same : -2). 

Why have 2 types? 

---

Google "2's Complement."

-a

[hithesh]

I know 2s complement.

Here's why I am unable understand signed type-

I have two std logic vectors - a and b , both 8 bit

Lets say a= -4 (1111 1100)  and b=  -5 (1111 1011)

If I compare  a and b  in unsiged, then b is greater than a.

But if they are signed type, then a should be greater than b. 

But I get the same result for both signed and unsigned.

I am using signed(a) to convert a to singed type.

Please correct me if I am wrong.