Simulation and Verification

[20050710212]

Hello,

When I am verifying the whether the statements in the process are executed in sequential, it generates a warning.

a is the input,                an  array (0 to 3) of std_logic_vector(3 downto 0);

b is the output,              an  array (0 to 3) of std_logic_vector(3 downto 0);

res_temp is a signal,  an  array (0 to 1) of std_logic_vector(3 downto 0);

Codes in process(rst, clk) are shown as below:

process(rst,clk)
begin
   if (rst='0') then 
   res_temp  <=  (others=>ZEROS);
   b                 <=  (others=>ZEROS);
  elsif (clk'event and clk='1') then
  b(0)                <=  a(0);

  b(1)                <=  a(1); 
  b(2)                <=  res_temp(0);

  b(3)                <=  res_temp(1);

  res_temp(0) <= a(2);

  res_temp(1) <= a(3);
end if;
end process;

When doing the simulation in modelsim, the results verified my guess. But when generating the post-synthesis simulation model in Xilinx ISE, there is a warning:

WARNING:NetListWriters:303 - Unable to preserve the ordering for port bus a on
block if_else_seq using the data a<0><3:0>.
WARNING:NetListWriters:303 - Unable to preserve the ordering for port bus b on
block if_else_seq using the data b<0><3:0>.

Could you tell me how to fix up this warning?

Thank you very much!

[graces]

Did you use XST as synthesis tool?

We have seen similar issue, and this is because the input edif does not have a statement on the port ordering of the bus so netegn is not able to resolve the ordering and thus not able to preserve it.

For example, tools are expecting fomat as the following

(port (array (rename a "a(3:0)") 4) (direction INPUT))

instead of

(port (array a 4) (direction INPUT))

If post-synthesis simulation runs well, you can just ignore the message.

[franciscoaiglesias]

Sorry to interrupt but what if the post PAR simulation goes wrong ?

I have a wired problem that I assuming is other thing but the only warning I've got is this one !!

THanks

[graces]

My understanding is you received the warning in generating post-synthesis simulation model.

Did you receive it in post-PAR simulation model generation?

Incorrect Post-PAR simulation could result from multiple factors: timing violation, incorrect logic introduced by MAP.

If these are all ruled out and you believe it has something to do with the warning, I suggest that you open a webcase with Xilinx Techincal Support.