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WARNING:Xs t:2170
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01-30-2011 12:46 PM
HI,
I am getting this warning though I have not created too many case states .There are only 4 case statements.
Solved! Go to Solution.
Re: WARNING:Xs t:2170
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01-30-2011 01:08 PM
The warnings you get have nothing to do with you having too many states (what makes you think that?). The real reason is that you did not use proper synchronous digital design techniques: your signal next_state is read and written to in a combinational circuit.
To see how a state machine has to be coded, open the Language Temples ==> Verilog/VHDL ==> Synthesis constructs ==> Coding examples ==> State machines.
Better yet, buy a book on your favorite HDL and read it thoroughly.
Adrian
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Re: WARNING:Xs t:2170
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01-31-2011 06:11 PM
Re: WARNING:Xs t:2170
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02-01-2011 10:44 AM
sneha22 wrote:
solved it..
And your solution was ... ??
----------------------------------------------------------------
Yes, I do this for a living.
Re: WARNING:Xs t:2170
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02-01-2011 12:24 PM
bassman59 wrote:
sneha22 wrote:
solved it..
And your solution was ... ??
...probably not to create a combinational loop.
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Re: WARNING:Xs t:2170
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02-02-2011 04:17 PM
Re: WARNING:Xs t:2170
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03-06-2012 12:43 AM
hello,
i have this warning in ISE 10.1, but it does not write any signals that form a combinatorial loop??!!
how i can find that signals?
thanks.
WARNING Xst :2170 :the following signal(s) form a combinatorial loop:
Re: WARNING:Xs t:2170
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01-11-2013 05:34 AM
If you don't see the signal involved in the combinational loop, it is just because you are viewing the design summary window. But if you switch to console or warnings panes (at the bottom of the main window) you will see the same messages but with the list of involved signals. Hope this helps.











