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Visitor
tcbriese
Posts: 3
Registered: ‎09-19-2008
0
Accepted Solution

Wanted: ISIM Verilog File IO Example

I have been designing FPGAs for a while, but exclusively in Modelsim.  I am trying to get fileIO working in ISIM with $fscanf or $fgetc.  Neither is working. 

 

I do get a non-zero file ID when using $fopen, so I believe it sees my file just fine.  Different read commands have different effects (sometimes the simulation runs endlessly, sometimes it returns a EOF right where the first read from file should occur).

 

Just wondered if someone had some example code and an example input file that works with ISIM.  Code for this that works in Modelsim is not working in ISIM for me.

 

Thanks!

 

- Thad

 

 

Regular Visitor
flosch
Posts: 34
Registered: ‎11-14-2012
0

Re: Wanted: ISIM Verilog File IO Example

Would also be interested in an example for reading a simple input file into my testbench.

Basically, I am trying to read an input vector from a file.

Here is my verilog minimal example code:

 

`timescale 1ns/1ns
module fir_filter_tb();
    
    //variables
    reg clk,rst;
    
    integer in,i;
    reg data;
    
    //generate clock
    always #5 clk = !clk;

    initial begin
        $monitor("data=%b",data);
        in = $fopen("fir_filter_input","rb");
        if(!in) $display("File Open Error!");
        
        i = $fscanf(in,"%b",data);
        $fclose(in);
    end
    
endmodule

 

The file filter_fir_input has the binary content

1
1
1
0
1

The input isn't read as the output of the monitor task is: data=x

I have also checked the linux access permissions and set them to chmod 777.

Besides $fscanf, both $readmemb or $readmemh is not working, too.

 

I searched the forum and the file read behaviour seems to behave a bit different, so a example code for the file read would be nice!

 

Thanks, Flo

Regular Visitor
flosch
Posts: 34
Registered: ‎11-14-2012
0

Re: Wanted: ISIM Verilog File IO Example

argh, missing the edit function in this forum.

just checked what value in got assigned and its -20000. its kinda weird, isn't it? Shouldn't it be any positive integer?
Regular Visitor
flosch
Posts: 34
Registered: ‎11-14-2012
0

Re: Wanted: ISIM Verilog File IO Example

I found out the solution. The file to read couldn't be found. Anyway, the input handle wasn't set to zero, so the "File Open Error"-if loop didn't match. Maybe that is a bug and should be checked.

For sake of completeness of this thread, here is a working minimal example that should help ppl encountering file reading issues:

 

`timescale 1ns/1ns
module test_tb();
	
	//variables
	reg clk,rst;
	
	integer in,i;
	reg data;
	
	//generate clock
	always #5 clk = !clk;

	initial begin 
		$monitor("data=%b,in=%d",data,in);
		in = $fopen("/your_absolute/file_path/file_to_read","rb");
		if(!in) $display("File Open Error!");
		
		i = $fscanf(in,"%b",data);
		$fclose(in);
	end
	
endmodule

 

Cheers, Flo