06-06-2012 02:27 PM
I have a project that uses multiple SERDES lines for high speed LVDS communication. I was able to simulate the project in ISIM using ISE 13.2 and 13.3. I added the programmable delay block in coregen to a few of the SERDES modules and now ISIM continuously elaborates and slows my computer to a halt. Any ideas why this would be happening?
Here is my port map
userDV_inst : serdes8t1_delay
-- From the device out to the system
DATA_OUT_FROM_DEVICE => dvDelayVectorEx,
DATA_OUT_TO_PINS_P => DataValidUser_p,
DATA_OUT_TO_PINS_N => DataValidUser_n,
-- Input, Output delay control signals
DELAY_RESET => dvDelayReset, -- Active high synchronous reset for input delay
DELAY_DATA_CE0 => '0', -- Enable signal for delay for bit 0
DELAY_DATA_INC0 => '0', -- Delay increment, decrement signal for bit 0
DELAY_TAP_IN0 => usr_DataValidDelayEx, -- Dynamically loadable delay tap value for bit 0
DELAY_TAP_OUT0 => open, -- Bit 0 Delay tap value for monitoring
DELAY_LOCKED => open, -- Locked signal from IDELAYCTRL
REF_CLOCK => io_delay_clk, -- Reference Clock for IDELAYCTRL. Has to come from BUFG.
-- Clock and reset signals
CLK_IN => clk400M,
CLK_DIV_IN => clk100M,
CLK_RESET => serdes_io_rst,
IO_RESET => DAC_serdes_rst(0)
06-06-2012 05:34 PM
This is typically seen in a large design. If possible, you could move to a 64-bit linux machine to see if it makes any difference.
Another way to try is to run simulation in interactive command line mode and then open the static simulation result in GUI.
In command line, cd to your project directory,
>isimgui.exe -view test_beh.wdb
06-07-2012 11:37 AM
I don't have a 64-bit Linux system to try this.
I did try from the command line with the same results - slows the machine down considerably with no indication that anything productive is happening for 10 minutes.
My project is not very large or complex. I'm using 80% of the memory and about 4-6% of the logic. It simulated fairly quickly without the delay elements in the SERDES and when I introduce the delay, it fails.
I don't understand why - unless I am not hooking something up properly.
06-07-2012 11:53 AM
To narrow down the problem, you could just simulate one of the blocks by itself. You don't need a testbench, just an instantiate and simulate the block. If the simulation fails then you have anrrowed down the problem to core or simulator and open a tech support case.
06-11-2012 12:49 PM
Here's a development...
I went back to a previous version of my project and found that if I set my preferred language to VHDL, then the simulation hangs in elaboration. It seems to work fine if it is set to Verilog. Please note that this is without the IODelays. It would seem that one or more of the cores I use fail in VHDL, but not in Verilog.
Below is a list of all the cores I use:
I also noticed that with 14.1, the Verilog and VHDL definitions do not match for the IODelayed SERDES.
Any ideas besides 'just use Verilog?'