Simulation and Verification

[dbasberg]

I am trying to read the help docs, but have not found how to see compiler errors.

I have had implement failures for sch to hdl and failures in iSIM to simulate (due to syntax errors in my test bench I assume.  I can not find the error messages.  Right clicking the 'simulate behavioral model provides 'text report' choice.  When I select that, I get no result.  If anyone can just give me a hint about what to read to learn about these things, that would be great.  I am willing to read and learn, but, so far, I have not found anything to help with this.

Thanks for any help.  BTW, when I get my syntax perfect, the tools work well.

[dbasberg · Accepted solution]

I found the answer myself.  I did more help searching for syntax error, compiler error, etc. and found that I had not enabled the panels for tcl console, errors, and warnings.  Turned those on and it showed me what my syntax error was and I was in business.  I have applied my test bench and verified my schematic/vhld.

Honest, I had tried to find the answer before I posted and only when I lost two days of progress on the progress, posted for help.