reading text file in isim12.3

technovlsi · ‎01-30-2011

sir, i havea doubt that is isim support text file included in the project during simulation. i heve used textio library,neccesary command to read and write the text file, but during simulation it gives error that isim could not found the text file. plz suggest me. if isim support it,then plz give the links of pdfs or website where i can learn the proper method.

thanks in advance.

evgenis1 · ‎12-03-2007

Hi,

You probably have an incorrect path to the text file relative to the directory simulation is running from. Try temporarily assigning an absolute path (c:\... on Windows or /... on Linux) to the text file to see if it's indeed the problem.

Another thing to try is to temporarily put the file in simulation directory, so that there is no absolute/relative path required.

Thanks,

Evgeni

technovlsi · ‎01-30-2011

evgenis1 wrote:

Hi,

You probably have an incorrect path to the text file relative to the directory simulation is running from. Try temporarily assigning an absolute path (c:\... on Windows or /... on Linux) to the text file to see if it's indeed the problem.

Another thing to try is to temporarily put the file in simulation directory, so that there is no absolute/relative path required.

Thanks,

Evgeni

sir, i have put the .txt file in simulation directory. but still i get the same error. what will i do?

evgenis1 · ‎12-03-2007

Can you post your code that opens and reads the file.

Evgeni

technovlsi · ‎01-30-2011

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use std.textio.all;
use IEEE.std_logic_textio.all;

entity tb_cfft1024x12 is

end tb_cfft1024x12;

architecture tb of tb_cfft1024x12 is

component cfft1024X12
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 invert : in std_logic;
                 Iin : in STD_LOGIC_VECTOR(11 downto 0);
                 Qin : in STD_LOGIC_VECTOR(11 downto 0);
                 inputbusy : out STD_LOGIC;
                 outdataen : out STD_LOGIC;
                 Iout : out STD_LOGIC_VECTOR(13 downto 0);
                 Qout : out STD_LOGIC_VECTOR(13 downto 0);
                 OutPosition : out STD_LOGIC_VECTOR( 9 downto 0 )
             );
end component;

signal  clk : STD_LOGIC;
signal  rst : STD_LOGIC;
signal  start : STD_LOGIC;
signal  invert : std_logic;
signal  Iin : STD_LOGIC_VECTOR(11 downto 0);
signal  Qin : STD_LOGIC_VECTOR(11 downto 0);
signal  inputbusy : STD_LOGIC;
signal  outdataen : STD_LOGIC;
signal  Iout : STD_LOGIC_VECTOR(13 downto 0);
signal  Qout : STD_LOGIC_VECTOR(13 downto 0);
signal  output_position:std_logic_vector(9 downto 0 );
constant clkprd : time:=10 ns;

begin
f: cfft1024x12 port map(clk=>clk,
                        rst =>rst,
                        start=> start,
                        invert=>invert,
                        Iin=>Iin,
                        Qin=>Qin,
                        inputbusy=>inputbusy,
                        outdataen=>outdataen,
                        Iout=>Iout,
                        Qout=>Qout,
                        OutPosition=>output_position);

clockgen: process
begin
        clk <= '1';
        wait for clkprd/2;
        clk <= '0';
        wait for clkprd/2;
end process;

fileread: process
file FileIn1 : text is in  "bindata"; -- bindata is a file containing 1-1024
in binary.
variable LineIn1   : line;
variable InputTmp1 :std_logic_vector(11 downto 0);
begin
                rst<='1';
                wait until clk'EVENT and clk='1';
                rst<='0';
                wait until clk'EVENT and clk='1';
                invert<='0';
                start<='1';
                wait until clk'EVENT and clk='1';
                start<='0';

                while  not( endfile( FileIn1)) loop
                        readline( FileIn1, LineIn1);
                        read(LineIn1, InputTmp1);
                        Iin<=InputTmp1;
                        Qin<="000000000000";
                        wait until clk'EVENT and clk='1';
                end loop;

                wait until outdataen'EVENT and outdataen='1';
                wait for 15000 ns;
end process;

end tb;

this is my test bench code sir. i have attach the .txt file as for reference of this code.