12-10-2008 12:31 PM
I created a ddr2 sdram interface with MIG and I'd like to simulate the example code that gets generated. I have Modelsim. MIG generates a vhdl testbench and a verilog model for the device. So, Modelsim is unable to simulate because you cannot have both vhdl and verilog parts. So, If I want my design to be in vhdl, then how can I simulate? I realize that there are free vhdl device models out there, but I don't know how to make them work with the testbench.