Simulation and Verification

[juansiahaan]

Hi everyone,

I'm making a code that receives a signal that has higher value than a comparator. If that condition is correct, a trigger will have a '1' value. This value is another condition to transfer the input to the output. However, before transferring, the input signal should be multiplied by a floating-point. I use the float-to-fixed from FP operator so that the floating point is converted into a fixed point. After the conversion is ready, the signal is multiplied. However, the result was always 0? I have two separate but similar codes for each modules (comparator and the receiver)...here is the code for the comparator...

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:17:31 05/16/2012 
-- Design Name: 
-- Module Name:    comparator_src - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comparator_src is
	PORT (CLK : in std_logic;
			RST : in std_logic;
			SDI0 : in std_logic;
			SDI1 : in std_logic;
			SDI2 : in std_logic;
			SDI3 : in std_logic;
			SDI4 : in std_logic;
			SDI5 : in std_logic;
			SDI6 : in std_logic;
			SDI7 : in std_logic;
			trigger0 : out std_logic := '0';
			trigger1 : out std_logic := '0'; 
			trigger2 : out std_logic := '0'; 
			trigger3 : out std_logic := '0'; 
			trigger4 : out std_logic := '0'; 
			trigger5 : out std_logic := '0'; 
			trigger6 : out std_logic := '0'; 
			trigger7 : out std_logic := '0'
			);
end comparator_src;

architecture Behavioral of comparator_src is

component Float_to_Fixed_convert_FP
	port (
	a: in std_logic_vector(31 downto 0);
	clk: in std_logic;
	sclr: in std_logic;
	ce: in std_logic;
	result: out std_logic_vector(11 downto 0);
	rdy: out std_logic);
end component;

signal buffer0 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer1 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer2 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer3 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer4 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer5 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer6 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer7 : std_logic_vector (11 downto 0) := (others => '0');
signal Q0 : std_logic_vector (11 downto 0) := (others => '0');
signal Q1 : std_logic_vector (11 downto 0) := (others => '0');
signal Q2 : std_logic_vector (11 downto 0) := (others => '0');
signal Q3 : std_logic_vector (11 downto 0) := (others => '0');
signal Q4 : std_logic_vector (11 downto 0) := (others => '0');
signal Q5 : std_logic_vector (11 downto 0) := (others => '0');
signal Q6 : std_logic_vector (11 downto 0) := (others => '0');
signal Q7 : std_logic_vector (11 downto 0) := (others => '0');

signal t0 : std_logic := '0';
signal t1 : std_logic := '0';
signal t2 : std_logic := '0';
signal t3 : std_logic := '0';
signal t4 : std_logic := '0';
signal t5 : std_logic := '0';
signal t6 : std_logic := '0';
signal t7 : std_logic := '0';

signal enable : std_logic := '0';
signal ready : std_logic := '0';
signal conv_rst : std_logic := '0';

constant comparator : std_logic_vector (31 downto 0) := "00111101110011001100110011001101";
signal converted_comparator : std_logic_vector (11 downto 0) := (others => '0');

begin
trigger0 <= t0;
trigger1 <= t1;
trigger2 <= t2;
trigger3 <= t3;
trigger4 <= t4;
trigger5 <= t5;
trigger6 <= t6;
trigger7 <= t7;
						
Comparator_conversion : Float_to_Fixed_convert_FP
		port map (
			a => Comparator,
			clk => CLK,
			sclr => conv_rst,
			ce => enable,
			result => converted_comparator,
			rdy => ready);
			
	compare : process (CLK)
	variable count : natural range 0 to 11 := 0;
	variable listen : natural range 0 to 27650 := 0;
	begin
	if rising_edge (CLK) then
		if RST = '1' then
			buffer0 <= (others => '0');
			buffer1 <= (others => '0');
			buffer2 <= (others => '0');
			buffer3 <= (others => '0');
			buffer4 <= (others => '0');
			buffer5 <= (others => '0');
			buffer6 <= (others => '0');
			buffer7 <= (others => '0');
			enable <= '0';
			count := 0;
		elsif listen <= 27600 then
			buffer0 <= buffer0 (10 downto 0) & SDI0;
			buffer1 <= buffer1 (10 downto 0) & SDI1;
			buffer2 <= buffer2 (10 downto 0) & SDI2;
			buffer3 <= buffer3 (10 downto 0) & SDI3;
			buffer4 <= buffer4 (10 downto 0) & SDI4;
			buffer5 <= buffer5 (10 downto 0) & SDI5;
			buffer6 <= buffer6 (10 downto 0) & SDI6;
			buffer7 <= buffer7 (10 downto 0) & SDI7;
			listen := listen + 1;
			if count = 11 then
				count := 0;
				enable <= '1';
				Q0 <= buffer0;
				Q1 <= buffer1;
				Q2 <= buffer2;
				Q3 <= buffer3;
				Q4 <= buffer4;
				Q5 <= buffer5;
				Q6 <= buffer6;
				Q7 <= buffer7;
				if ready = '1' then
					If Q0 > converted_comparator then
						t0 <= '1';
						if (t0 = '1') then
							t0 <= '0';
						end if;
					elsif Q1 > converted_comparator then
						t1 <= '1';
						if (t1 = '1') then
							t1 <= '0';
						end if;
					elsif Q2 > converted_comparator then
						t2 <= '1';
						if (t2 = '1') then
							t2 <= '0';
						end if;
					elsif Q3 > converted_comparator then
						t3 <= '1';
						if (t3 = '1') then
							t3 <= '0';
						end if;
					elsif Q4 > converted_comparator then
						t4 <= '1';
						if (t4 = '1') then
							t4 <= '0';
						end if;
					elsif Q5 > converted_comparator then
						t5 <= '1';
						if (t5 = '1') then
							t5 <= '0';							
						end if;
					elsif Q6 > converted_comparator then
						t6 <= '1';
						if (t6 = '1') then
							t6 <= '0';
						end if;
					elsif Q7 > converted_comparator then
						t7 <= '1';
						if (t7 = '1') then
							t7 <= '0';
						end if;
					else
						t0 <= '0';
						t1 <= '0';
						t2 <= '0';
						t3 <= '0';
						t4 <= '0';
						t5 <= '0';
						t6 <= '0';
						t7 <= '0';
					end if;
				end if;
			else
				count := count + 1;
				enable <= '0';
			end if;
		elsif listen > 27600 then
			Q0 <= (others => '0');
			Q1 <= (others => '0');
			Q2 <= (others => '0');
			Q3 <= (others => '0');
			Q4 <= (others => '0');
			Q5 <= (others => '0');
			Q6 <= (others => '0');
			Q7 <= (others => '0');
			enable <= '0';
			conv_rst <= '1';
			t0 <= '0';
			t1 <= '0';
			t2 <= '0';
			t3 <= '0';
			t4 <= '0';
			t5 <= '0';
			t6 <= '0';
			t7 <= '0';
		end if;
	end if;
	end process compare;

end Behavioral;

  and this is the code for my receiver...

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:40:55 05/14/2012 
-- Design Name: 
-- Module Name:    delay_sum_beamforming_src - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: This code is the other version of the previos one (dsb_src)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--library ieee_proposed;
--use ieee_proposed.fixed_pkg.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity delay_sum_beamforming_src is
	PORT (CLK : in std_logic;
			RST : in std_logic;
			SDI0 : in std_logic;
			SDI1 : in std_logic;
			SDI2 : in std_logic;
			SDI3 : in std_logic;
			SDI4 : in std_logic;
			SDI5 : in std_logic;
			SDI6 : in std_logic;
			SDI7 : in std_logic;
			Frame : in std_logic;
			ws0 : out std_logic_vector (23 downto 0) := (others => '0');
			ws1 : out std_logic_vector (23 downto 0) := (others => '0');
			ws2 : out std_logic_vector (23 downto 0) := (others => '0');
			ws3 : out std_logic_vector (23 downto 0) := (others => '0');
			ws4 : out std_logic_vector (23 downto 0) := (others => '0');
			ws5 : out std_logic_vector (23 downto 0) := (others => '0');
			ws6 : out std_logic_vector (23 downto 0) := (others => '0');
			ws7 : out std_logic_vector (23 downto 0) := (others => '0');
--			summed : out std_logic_vector (11 downto 0) := (others => '0');
			ND : out std_logic := '0'
			);
end delay_sum_beamforming_src;

architecture Behavioral of delay_sum_beamforming_src is

--Comparator
COMPONENT comparator_src
	PORT(
		CLK : IN std_logic;
		RST : IN std_logic;
		SDI0 : IN std_logic;
		SDI1 : IN std_logic;
		SDI2 : IN std_logic;
		SDI3 : IN std_logic;
		SDI4 : IN std_logic;
		SDI5 : IN std_logic;
		SDI6 : IN std_logic;
		SDI7 : IN std_logic;          
		trigger0 : OUT std_logic;
		trigger1 : OUT std_logic;
		trigger2 : OUT std_logic;
		trigger3 : OUT std_logic;
		trigger4 : OUT std_logic;
		trigger5 : OUT std_logic;
		trigger6 : OUT std_logic;
		trigger7 : OUT std_logic
		);
	END COMPONENT;

--float to fixed converted
component Float_to_Fixed_IP
	port (
	a: in std_logic_vector(31 downto 0);
	clk: in std_logic;
	ce: in std_logic;
	result: out std_logic_vector(11 downto 0);
	rdy: out std_logic);
end component;

--multiplier
COMPONENT weighting_IP
  PORT (
    clk : IN STD_LOGIC;
    a : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    b : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
    ce : IN STD_LOGIC;
    p : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
  );
END COMPONENT;

--signals for dsb
signal framex : std_logic; -- for Frame
signal enable : std_logic := '0'; -- for conversion
signal ready_convert0 : std_logic := '0'; --for conversion
signal ready_convert1 : std_logic := '0';
signal ready_convert2 : std_logic := '0';
signal ready_convert3 : std_logic := '0';
signal ready_convert4 : std_logic := '0';
signal ready_convert5 : std_logic := '0';
signal ready_convert6 : std_logic := '0';
signal ready_convert7 : std_logic := '0';

signal enable1 : std_logic := '0'; --for weighting

signal buffer0 : std_logic_vector (11 downto 0) := (others => '0'); --buffers from SDI0 until SDI7
signal buffer1 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer2 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer3 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer4 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer5 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer6 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer7 : std_logic_vector (11 downto 0) := (others => '0');

signal trigger0 : std_logic := '0';-- declaration for peak detection block
signal trigger1 : std_logic := '0';
signal trigger2 : std_logic := '0';
signal trigger3 : std_logic := '0';
signal trigger4 : std_logic := '0';
signal trigger5 : std_logic := '0';
signal trigger6 : std_logic := '0';
signal trigger7 : std_logic := '0';

signal Q0 : std_logic_vector (11 downto 0) := (others => '0');-- for entering IP
signal Q1 : std_logic_vector (11 downto 0) := (others => '0');
signal Q2 : std_logic_vector (11 downto 0) := (others => '0');
signal Q3 : std_logic_vector (11 downto 0) := (others => '0');
signal Q4 : std_logic_vector (11 downto 0) := (others => '0');
signal Q5 : std_logic_vector (11 downto 0) := (others => '0');
signal Q6 : std_logic_vector (11 downto 0) := (others => '0');
signal Q7 : std_logic_vector (11 downto 0) := (others => '0');

--constants for signal weighting
constant w0 : std_logic_vector (31 downto 0) := "00111000100000100011101110101111";
constant w1 : std_logic_vector (31 downto 0) := "00111000100011110111000111111000";
constant w2 : std_logic_vector (31 downto 0) := "00111000101001010111011100011101";
constant w3 : std_logic_vector (31 downto 0) := "00111000110001001000000011001110";
constant w4 : std_logic_vector (31 downto 0) := "00111000111011001111101001101010";
constant w5 : std_logic_vector (31 downto 0) := "00111001000011101001101100111001";
constant w6 : std_logic_vector (31 downto 0) := "00111001001011010000001111011010";
constant w7 : std_logic_vector (31 downto 0) := "00111001010011101001000111001001";
--end constants for signal weighting

--converted floating point
signal c0 : std_logic_vector (11 downto 0) := (others => '0');
signal c1 : std_logic_vector (11 downto 0) := (others => '0');
signal c2 : std_logic_vector (11 downto 0) := (others => '0');
signal c3 : std_logic_vector (11 downto 0) := (others => '0');
signal c4 : std_logic_vector (11 downto 0) := (others => '0');
signal c5 : std_logic_vector (11 downto 0) := (others => '0');
signal c6 : std_logic_vector (11 downto 0) := (others => '0');
signal c7 : std_logic_vector (11 downto 0) := (others => '0');
--end converted floating point

begin
Inst_comparator_src: comparator_src PORT MAP(
		CLK => CLK,
		RST => RST,
		SDI0 => SDI0,
		SDI1 => SDI1,
		SDI2 => SDI2,
		SDI3 => SDI3,
		SDI4 => SDI4,
		SDI5 => SDI5,
		SDI6 => SDI6,
		SDI7 => SDI7,
		trigger0 => trigger0,
		trigger1 => trigger1,
		trigger2 => trigger2,
		trigger3 => trigger3,
		trigger4 => trigger4,
		trigger5 => trigger5,
		trigger6 => trigger6,
		trigger7 => trigger7
	);

Convert0 : Float_to_Fixed_IP
		port map (
			a => w0,
			clk => CLK,
			ce => enable,
			result => c0,
			rdy => ready_convert0);
			
Weighting0 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c0,
    b => Q0,
    ce => enable1,
    p => ws0
  );			

Convert1 : Float_to_Fixed_IP
		port map (
			a => w1,
			clk => CLK,
			ce => enable,
			result => c1,
			rdy => ready_convert1);
			
Weighting1 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c1,
    b => Q1,
    ce => enable1,
    p => ws1
  );

Convert2 : Float_to_Fixed_IP
		port map (
			a => w2,
			clk => CLK,
			ce => enable,
			result => c2,
			rdy => ready_convert2);
			
Weighting2 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c2,
    b => Q2,
    ce => enable1,
    p => ws2
  );	

Convert3 : Float_to_Fixed_IP
		port map (
			a => w3,
			clk => CLK,
			ce => enable,
			result => c3,
			rdy => ready_convert3);

Weighting3 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c3,
    b => Q3,
    ce => enable1,
    p => ws3
  );
			
Convert4 : Float_to_Fixed_IP
		port map (
			a => w4,
			clk => CLK,
			ce => enable,
			result => c4,
			rdy => ready_convert4);
			
Weighting4 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c4,
    b => Q4,
    ce => enable1,
    p => ws4
  );

Convert5 : Float_to_Fixed_IP
		port map (
			a => w5,
			clk => CLK,
			ce => enable,
			result => c5,
			rdy => ready_convert5);
			
Weighting5 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c5,
    b => Q5,
    ce => enable1,
    p => ws5
  );
			
Convert6 : Float_to_Fixed_IP
		port map (
			a => w6,
			clk => CLK,
			ce => enable,
			result => c6,
			rdy => ready_convert6);
			
Weighting6 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c6,
    b => Q6,
    ce => enable1,
    p => ws6
  );
			
Convert7 : Float_to_Fixed_IP
		port map (
			a => w7,
			clk => CLK,
			ce => enable,
			result => c7,
			rdy => ready_convert7);	

Weighting7 : weighting_IP
  PORT MAP (
    clk => CLK,
    a => c7,
    b => Q7,
    ce => enable1,
    p => ws7
  );
			
	--main process
	dsb : process (CLK)
	variable count : std_logic_vector (3 downto 0) := (others => '0');
	variable listen_time : natural range 0 to 276500 := 0;
	begin
		if rising_edge (CLK) then
		framex <= Frame;
			if RST = '1' then
				count := (others => '0');
				listen_time := 0;
				ND <= '0';
				enable <= '0';
				buffer0 <= (others => '0');
				buffer1 <= (others => '0');
				buffer2 <= (others => '0');
				buffer3 <= (others => '0');
				buffer4 <= (others => '0');
				buffer5 <= (others => '0');
				buffer6 <= (others => '0');
				buffer7 <= (others => '0');		
			elsif (trigger0 = '1' or trigger1 = '1' or trigger2 = '1' or trigger3 = '1' or trigger4 = '1' or trigger5 = '1' or trigger6 = '1' or trigger7 = '1') then
					if listen_time <= 276000 then
						buffer0 <= buffer0 (10 downto 0) & SDI0;
						buffer1 <= buffer1 (10 downto 0) & SDI1;
						buffer2 <= buffer2 (10 downto 0) & SDI2;
						buffer3 <= buffer3 (10 downto 0) & SDI3;
						buffer4 <= buffer4 (10 downto 0) & SDI4;
						buffer5 <= buffer5 (10 downto 0) & SDI5;
						buffer6 <= buffer6 (10 downto 0) & SDI6;
						buffer7 <= buffer7 (10 downto 0) & SDI7;
						listen_time := listen_time + 1;
						count := count + 1;
						if count = 11 then
							count := (others => '0');
							enable <= '1';
							if trigger0 = '1' then
								Q0 <= buffer0;
							else
								Q0 <= (others => '0');
							end if;
							if trigger1 = '1' then
								Q1 <= buffer1;
							else
								Q1 <= (others => '0');
							end if;
							if trigger2 = '1' then
								Q2 <= buffer2;
							else
								Q2 <= (others => '0');
							end if;
							if trigger3 = '1' then
								Q3 <= buffer3;
							else
								Q3 <= (others => '0');
							end if;
							if trigger4 = '1' then
								Q4 <= buffer4;
							else
								Q4 <= (others => '0');
							end if;
							if trigger5 = '1' then
								Q5 <= buffer5;
							else
								Q5 <= (others => '0');
							end if;
							if trigger6 = '1' then
								Q6 <= buffer6;
							else
								Q6 <= (others => '0');
							end if;
							if trigger7 = '1' then
								Q7 <= buffer7;
							else
								Q7 <= (others => '0');
							end if;
						else
							enable <= '0';
						end if;
					elsif listen_time > 276000 then
							Q0 <= (others => '0');
							Q1 <= (others => '0');
							Q2 <= (others => '0');
							Q3 <= (others => '0');
							Q4 <= (others => '0');
							Q5 <= (others => '0');
							Q6 <= (others => '0');
							Q7 <= (others => '0');
							enable <= '0';
							count := (others => '0');
							if (framex = '0' and Frame = '1') then
								ND <= '1';
							else
								ND <= '0';
							end if;
					end if;
				end if;
			end if;
	end process dsb;
			
	--weighting process
	weighting : process (ready_convert1, ready_convert2, ready_convert3, ready_convert4, ready_convert5, ready_convert6, ready_convert7)
	begin
		if (ready_convert1 = '1' or ready_convert2 = '1' or ready_convert3 = '1' or ready_convert4 = '1' or ready_convert5 = '1' or ready_convert6 = '1' or ready_convert7 = '1') then
			enable1 <= '1';
		else
			enable1 <= '0';
		end if;
	end process weighting;
	
end Behavioral;

  And the simulation result is in the attachments (the 1st one is for the comparator and the 2nd one is for the receiver)

[juansiahaan]

And this is for the receiver...

I only tested 1 input because I think the other inputs can follow...and for information, the synthesize summary report didn't give any warning messages...

[rourabpaul]

I think you have made some mistake in testbench