Spartan® Family FPGAs

[keep28]

Hi,

Ive got a design that uses a spartan XC3S500E, but when I populate
the design with the smaller, but what I thought was compatible XC3S250E and generate a
bit stream to suit, it fails to program the SPI flash. With a .BIT
and a .MCS (which works correctly when you download it direct to the
250E), it fails to program the external M25P80 SPI flash
using iMPACT 10.1 and a Platform Cable USB II jtag adaptor.

The error message I get with two different identical boards, is a
failure at address 0 (board A) and failure at address 1024 (board B)
I have replaced the M25P80 flash memories on both boards as a sanity check, but no dice.

The very same exact design works perfectly with 4 other boards, identical,
except populated with the 500E instead.

Anyone have any idea's on what I could be doing wrong?

Is there a bug in xc3s250e_spi.cor?

many thanks,

steve

IMPACT 10.1 message window dump

PROGRESS_START - Starting Operation.
Identifying chain contents ....'1': : Manufacturer's ID =Xilinx
xc3s250e, Version : 1
INFO:iMPACT:1777 -
Reading C:/Xilinx/10.1/ISE/spartan3e/data/xc3s250e.bsd...
INFO:iMPACT:501 - '1': Added Device xc3s250e successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
PROGRESS_END - End Operation.
Elapsed time =      1 sec.
// *** BATCH CMD : identifyMPM
// *** BATCH CMD : assignFile -p 1 -file "C:/250test.bit"
'1': Loading file 'C:/250test.bit' ...
done.
INFO:iMPACT:501 - '1': Added Device xc3s250e successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Selected part: M25P80
// *** BATCH CMD : attachflash -position 1 -spi "M25P80"
// *** BATCH CMD : assignfiletoattachedflash -position 1 -file "C:/
250etest.mcs"
// *** BATCH CMD : attachflash -position 1 -spi "M25P80"
// *** BATCH CMD : Program -p 1 -spionly -e -v
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': SPI access core not detected. SPI access core will be downloaded
to the device to enable operations.
INFO:iMPACT - Downloading core file C:/Xilinx/10.1/ISE/spartan3e/data/
xc3s250e_spi.cor.
PROGRESS_START - Starting Operation.
'1': Downloading core...
done.
'1': Reading status register contents...
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 0111 1001 1000 0000 0000 0000 0000
INFO:iMPACT:2492 - '1': Completed downloading core to device.
INFO:iMPACT - '1': Checking done pin....done.
'1': Core downloaded successfully.
'1': IDCODE is '13' (in hex).
'1': ID Check passed.
 '1': IDCODE is '13' (in hex).
'1': ID Check passed.
 '1': Erasing Device.
'1': Programming Flash.
'1': Reading device contents...
Failed at address, 0
'1': Verification Terminated
PROGRESS_END - End Operation.
Elapsed time =     19 sec.

[bassman59]

If I read you correctly, you're trying to load a 500E bitstream into the 250E part.

You can't do that.

[keep28]

"but what I thought was compatible XC3S250E and generate a
bit stream to suit,"

This means I generated a bit stream to suit a 250E. ie - a .BIT and .MCS to suit the new 250E target.

So, no - we are not trying to squeeze a 500E bit stream into a 250E.

[drjohnsmith]

What foot print are the two chips ?

[keep28]

Both devices are PQ208's with exactly the same pinout. Infact, the same pinout section in DS312 is used to describe both devices.

In the xilinx document DS312, it states on page 189;

"The XC3S250E and XC3S500E FPGAs have identical footprints in the PQ208 package. Designs can migrate between the XC3S250E and XC3S500E without further consideration."

However, in my design - this is not happening. The only difference between the two boards of the same design is;

a) One is populated with a 500E. The other is populated with a 250E

b) For the 250E, the design has been re-synthesised and routed to suit a 250E (given)

c) The Xilinx SPI bridge core is different (used from C:/Xilinx/10.1/ISE/spartan3e/data/xc3s250e_spi.cor.)

Downloading the 250E bitstream direct to the FPGA via JTAG produces a functional design. Downloading the 250E bitstream to the SPI flash of the 250E fails via the xilinx xc3s250e_spi.cor.

However, these steps both work correctly with the 500E and the 500E's SPI bridge core.

[drjohnsmith]

Well,

Sorry, you've reached my limits,

the only obvious difference is the spi module, but I can't see how that is wrong.

  have you tries re compiling form fresh the 500 and the 250 design, just in case it's a duff UCF.

Have you double checked for solder shorts, I'm certain you have but I'm scratching head here.

I know there were some problems years back with pre version of the Spartans before stepping 1 and SPI, but I can't imagine you have old silicon and I dont seems to remember this was the problem.

I'd try asking a web case, see where you get. 

[keep28]

Hi,

Well,

Sorry, you've reached my limits,

--> Thanks for taking the time to read my problem an express your idea's. This helps me make sure I have covered all my bases too.

the only obvious difference is the spi module, but I can't see how that is wrong.

--> Well - it is a completely different silicon device. Knowing Xilinx, they forgot something obvious, like current drive on an output or something. Only a minor difference is enough to stop it (that is, if it is the core)

have you tries re compiling form fresh the 500 and the 250 design, just in case it's a duff UCF.

--> Yep, and both images work fine, including the 250E - the design works a treat in the FPGA - but only when you download it via JTAG into the device. Its when you try to write the image to the SPI flash on the 250E that it wont write - correct id etc, but fails at add 0. I also found that xilinx impact 10 returns the correct device ID (in my case a 25P80 is hex 13) if the device is there or not! (ie - the response is from the spi core, and not the actual flash chip)

Have you double checked for solder shorts, I'm certain you have but I'm scratching head here.

--> Yep. total checks under the scope. However, with the design working fine - there's no real need too, as it all works correctly. I did build many test projects to test all the hardware to see if i could sniff something out - which tested fine, including the flash - but, it just wont write to the flash when under the control of impact 10 with the xilinx spi bridge.

I know there were some problems years back with pre version of the Spartans before stepping 1 and SPI, but I can't imagine you have old silicon and I dont seems to remember this was the problem.

--> I hope not. they came from American II electronics , who have heaps in stock. Ill have to check the number. Do you know what sort of problems they had?

I'd try asking a web case, see where you get. 

--> I tried that, but since I dont have a corporate email address in my profile, xilinx will not let me log a case.

steve

[barriet]

I don't immediately have any suggestions...

But it may be worth noting that:

-the Stepping 0 and 1 differences are outlined in the datasheet (ds312.pdf)

-America II is not an authorized distributor:

http://www.xilinx.com/company/sales/ww_disti.htm

http://www.americaii.com/solutions/excessinventory.shtml

bt

[drjohnsmith]

An interesting supplier,

it might be worth while checking the steppings of the FPGA's. 

the stepping 0 parts had a great errata I seem to remember.

I hope you don't have stepping 0 for some of the chips. 

[keep28]

thats scary..

I took a look and I dont belive its a stepping 0 though. But if you could confirm from a xilinx perspective, that would be greatly appreciated.

The identification printed on the device is;

XILINX SPARTAN

XC3S250E

PQG208DGQ0733

D1466699A1

4C

Steve