05-26-2012 10:40 AM
The clock is one and only one. Nothing is added. I am just using crystal oscillator instead of MCU output for the clock. Everything else is the same as it was before. This way everything can be attached to it, form PIC16 to RX620, as long as it can output the address and data lines and read a wait signal from the FPGA. And the wait signal is only used if the MCU is reading from the frame buffer. If it doesn't have to read the frame buffer, then even the wait signal does not matter.
06-01-2012 03:34 AM
Could someone please explain the following:
This does not simulate, just as expected - if clocks (clock2x and mcu_wr_n) are asynchronows to each other, sooned or later the value of mcu_wr_n happens to be unknown (edge violates setup and hold times) at the edge of clock2x. In real life this will not be a problem, because if edge is not detected on one clock edge of clock2x, it will be detected on next edge anyway. So it is usable for simulation if synchronows clocks are used to simulate:
reg [1:0] mcu_wrreq_s; wire mcu_wren = mcu_wrreq_s == 2'b01; //synchonous mcu write request always @ (posedge mcu_wr_n) //register mcu write data and address begin if (~mcu_cs_n) begin mcu_addrwr <= mcu_addr; mcu_datawr <= mcu_data; mcu_b0wr <= mcu_b0_n; mcu_b1wr <= mcu_b1_n; end end always @ (posedge clock2x) //register mcu write request begin mcu_wrreq_s <= mcu_wrreq_s; mcu_wrreq_s <= mcu_wr_n; end
But this code simulates properly, no matter if mcu_wr_n clock is synchronous or asynchronows to clock2x:
reg [1:0] mcu_wrreq_s; wire mcu_wren = mcu_wrreq_s == 2'b01; //synchronous mcu write request always @ (posedge mcu_wr_n) //register mcu write data and address begin if (~mcu_cs_n) begin mcu_addrwr <= mcu_addr; mcu_datawr <= mcu_data; mcu_b0wr <= mcu_b0_n; mcu_b1wr <= mcu_b1_n; end end always @ (posedge clock2x) //mcu write request is registered here begin mcu_wrreq_s <= mcu_wrreq_s; if (mcu_wrreq_s != mcu_wr_n) mcu_wrreq_s <= ~mcu_wrreq_s end
This basically does the same thing, but instead of registering mcu_wr_n signal, it inverts mcu_wrreq_s if it is different to mcu_wr_n. However, mcu_wr_n can be undefined at that exact moment, but still it simulates without giving "X" state to mcu_wrreq_s.
My only explanation is that when mcu_wr_n violates the setup/hold times from clock2x's point of view, the simulator treats mcu_wr_n as "X" state, but comparing it to mcu_wrreq_s register, it threats it as a value, different than 0 or 1, so it inverts the mcu_wrreq_s anyway, despite the violation of setup/hold requirements.
Am I thinking right? Also, I think in real life both will work equally well. Am I right?
06-05-2012 10:18 AM
I just found out that the above approach does not work under ModelSim SE, so I guess it is a simulator setting or issue.
Trust the simulator.
You have a problem with your code.
Yes, I do this for a living.
06-08-2012 05:54 AM
Another question. As far as I can understand reading the configuration user guide, when using internal flash of the spartan 3an, the only pins that are necessary for programming are the 3 config (only on startup) + 4 JTAG pins. So, 105 out of 108 IO pins are available for IO (all 108 after startup). The design is entirely 3.3V LVTTL/LVCMOS33.
Is that right? Is there any other specifics to consider while designing the PCB?