Spartan® Family FPGAs

[safwenets]

Hi all,

I have implemented an I2C Interface on a SPARTAN6 LX45T FPGA. The FPGA commands a slave temperature sensor (AD7415 from Analog Devices).
When I tried to visualise the SCL and SDA signals with Chipscope, I discovered that the sensor is not acknowledging.
I tried to visualise these signals at the pins of the sensor with an oscilloscope and I found that the Input Low Voltage is higher than the allowed maximum voltage (which is 0.8V according to the sensor datasheet) .
The measured Input Low Voltage is 1V that means that zeros cannot be detected as all trasnmitted bits are interpreted as "1". I have to say that the FPGA is delivering a signal with 3.3V.
As you can see from the figure, the SCL signal(as well as the SDA) is shifted to the top. I don't know if this is due to the pull up resistors connected to the SDA and SCL buses? 
AD7415 sensor datasheet: http://www.analog.com/static/imported-files/data_sheets/AD7414_7415.pdf.
Could you please help me, thank you!

[eteam00]

You should post your schematics, and describe what troubleshooting steps you have already taken (and their results).

There are a number of possible causes...  Here are a few which come to mind:

• Defective I2C slave device (experiment: cut trace or lift pin to remove load pin from the trace).
• Defective or incorrect pullup R (verify pullup R value -- 10K?), and pullup R voltage.
• Incorrect FPGA output drive selection (should be LVCMOS33 or -- Spartan-6 only -- I2C, nominally 8mA).
• Short circuit on the board. (Set scope trigger to 0.5V -- does signal ever reach 0.5V?)
• Short circuit on the board (if you short the trace to GND through a 100-ohm R, what is V drop across the 100-ohm R?)
• Poor (high resistance) solder connection to the output driver.
• Incorrect 'scope setup (verify that GND is indeed 0V level on scope display)
• Design error (check device pinouts one more time)
• Poor connection on slave device (is slave device GND pin soldered correctly?)
• Assembly error (device misaligned to board pads -- do you have a second board for comparison?)

Once you find the problem, it will likely be something quite simple and obvious.  Unfortunately, the problem will be found in the last (not first) place you look.

-- Bob Elkind

[safwenets]

I simulated my vhdl code and it seems correct. Then I started verifiying the module with chipscope. I am not receiving the acknowledge bit after sending the first byte (7  bits for the address + write bit). Then I decided to chek the signals with a scope. Here is the shematic of my circuit. The pull up resistors are 10k (they are not 1K as mentionned in the schematic) and the VDD is equal to 3.3V(it is not 5V as mentionned in the schematic). As I have mentioned in my last post, SDA and SCL signals are shifted so that bits(zeros) are not received correctly. The problem seems to be physical and not logical.

[eteam00]

I am guessing that you are relatively new to the work of troubleshooting a circuit board design.  Suggest you step through the debugging experiments in my previous post.

The schematic you posted is almost useless.  The information which is important includes:

• device pin -- did you get the pinout correct?
• all connections to the interface signals -- including the I2C master (the FPGA!) and the other slaves
• power supply voltages and connections (to the master and to the slaves)
• pullups, pulldowns, diode clamps, terminations, etc. etc.

In short, the schematic should include the information you would think interesting for your own debugging effort.

If the temp sensor is connected to the FPGA board through a cable and connectors

• Have you measured the resistance between GND on the FPGA board and GND on the temp sensor board?
• Is there a direct connection of the GNDs of the two boards?

-- Bob Elkind

[bassman59]

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safwenets wrote:

I simulated my vhdl code and it seems correct. Then I started verifiying the module with chipscope. I am not receiving the acknowledge bit after sending the first byte (7  bits for the address + write bit). Then I decided to chek the signals with a scope. Here is the shematic of my circuit. The pull up resistors are 10k (they are not 1K as mentionned in the schematic) and the VDD is equal to 3.3V(it is not 5V as mentionned in the schematic). As I have mentioned in my last post, SDA and SCL signals are shifted so that bits(zeros) are not received correctly. The problem seems to be physical and not logical.

---

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safwenets wrote:

I simulated my vhdl code and it seems correct. Then I started verifiying the module with chipscope. I am not receiving the acknowledge bit after sending the first byte (7  bits for the address + write bit). Then I decided to chek the signals with a scope. Here is the shematic of my circuit. The pull up resistors are 10k (they are not 1K as mentionned in the schematic) and the VDD is equal to 3.3V(it is not 5V as mentionned in the schematic). As I have mentioned in my last post, SDA and SCL signals are shifted so that bits(zeros) are not received correctly. The problem seems to be physical and not logical.

---

Pull-up values for a 3.3V I2C bus are generally 2k instead of the 4.7k used for a 5V bus. 10K is too weak; the bus may not pull up to a valid logic level in  time.

Having said that -- the DC offset is weird. Are the converter and the FPGA on the same circuit board? My guess is that they are not. 

[gszakacs]

When I see an incorrect voltage like this, the first thing I do is to get out an Ohm-meter

and measure from the net to the power rail.  Maybe youre "10K" resistors are 10 Ohms,

or maybe there are other devices connected to the net by mistake (or by solder short).

-- Gabor

[safwenets]

What do you mean by "converter"?

[eteam00]

What do you mean by "converter"?

He probably meant to refer to your temperature sensor.  Brain sometimes runs on auto-pilot.  I2C and SPI interfaces to A/D converters is a common forum topic.

-- Bob Elkind

[safwenets]

ok, they are not in the same board...

[eteam00]

Did you read my comments in post #4?

-- Bob Elkind