Spartan® Family FPGAs

[cosmiac]

Im having trouble figuring out if there is a single-ended output that can be tied to a clock on this FPGA that is 1.6V or less. The only output i see on the board is a SMA differential pair, but i don't think I can use one of those connectors to create a single-ended clock output (If i am wrong about this please let me know) Here is the link to the Clocking resources for the board and the User Guide is attached.

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

[eteam00]

Im having trouble figuring out if there is a single-ended output that can be tied to a clock on this FPGA

What does "tied to a clock" mean?

that is 1.6V or less.

Do you mean to say that the FPGA output swing must be no more than 1.6V?  Or so you mean to say that the input to the FPGA has a logic swing of 1.6V or less?

The only output i see on the board is a SMA differential pair, but i don't think I can use one of those connectors to create a single-ended clock output.

See Figure 22 of the User Guide attached to your post.  There are many Bank 0 connections to the FMC connector which are highly configurable and customisable.  Differential pairs do not need to be configured as differential pairs in most cases... they can also be configured as single-ended signals.

-- Bob Elkind

[cosmiac]

When I connected my clock signal to one of the two SMA clock outputs I got an error, which is long gone as of now but I could recreate it if you want. Is there some constraint I need to include to declare that pin as a single-ended output? I need to output my clock so that it will also be the clock for the ADC I'm working with.

"Tied to a clock" means in VHDL the clock will be connected a top-level output and then in the constraints file it will be connected to a single-ended pin that I can then connect to the ADC clock input.

Could you please explain what the output swing and logic swing means? When I refer to the schematic for the board I can only access single-ended pins that are connected to banks at voltages of 2.5V and 3.3V but the ADC clock input doubles the input voltage and the ADC chip datasheet says that the maximum voltage for the clock is 3.5V.

Thanks for your help.

[cosmiac]

When I connected my clock signal to one of the two SMA clock outputs I got an error, which is long gone as of now but I could recreate it if you want. Is there some constraint I need to include to declare that pin as a single-ended output? I need to output my clock so that it will also be the clock for the ADC I'm working with.

"Tied to a clock" means in VHDL the clock will be connected a top-level output and then in the constraints file it will be connected to a single-ended pin that I can then connect to the ADC clock input.

Could you please explain what the output swing and logic swing means? When I refer to the schematic for the board I can only access single-ended pins that are connected to banks at voltages of 2.5V and 3.3V but the ADC clock input doubles the input voltage and the ADC chip datasheet says that the maximum voltage for the clock is 3.5V.

Thanks for your help.

[bassman59]

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cosmiac wrote:

When I connected my clock signal to one of the two SMA clock outputs I got an error, which is long gone as of now but I could recreate it if you want. Is there some constraint I need to include to declare that pin as a single-ended output? I need to output my clock so that it will also be the clock for the ADC I'm working with.

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There is no such thing as a "dedicated clock output." To the FPGA pins, a clock output is exactly like any other output. You have to set the proper IOSTANDARD (and perhaps instantiate a differential output buffer), slew rate, drive strength, etc. But that is true for any use of a signal.

Why do people think that there are special clock output pins? Nowhere in any of the literature is that suggested or implied.

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"Tied to a clock" means in VHDL the clock will be connected a top-level output and then in the constraints file it will be connected to a single-ended pin that I can then connect to the ADC clock input.

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So I must assume that you generate the "ADC clock output" inside the FPGA and you want to drive it out to the ADC using a pin that just happens to connect to one of the SMA connectors? See my paragraph above.

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Could you please explain what the output swing and logic swing means? When I refer to the schematic for the board I can only access single-ended pins that are connected to banks at voltages of 2.5V and 3.3V but the ADC clock input doubles the input voltage and the ADC chip datasheet says that the maximum voltage for the clock is 3.5V.

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That question is absolutely Electrical Engineering 101, as basic as you can get. Have you taken any EE courses?

What is mean by the "ADC clock input doubles the input voltage?" I've never heard of such a thing.

[bassman59]

When I connected my clock signal to one of the two SMA clock outputs I got an error, which is long gone as of now but I could recreate it if you want. Is there some constraint I need to include to declare that pin as a single-ended output? I need to output my clock so that it will also be the clock for the ADC I'm working with.

---

There is no such thing as a "dedicated clock output." To the FPGA pins, a clock output is exactly like any other output. You have to set the proper IOSTANDARD (and perhaps instantiate a differential output buffer), slew rate, drive strength, etc. But that is true for any use of a signal.

Why do people think that there are special clock output pins? Nowhere in any of the literature is that suggested or implied.

---

"Tied to a clock" means in VHDL the clock will be connected a top-level output and then in the constraints file it will be connected to a single-ended pin that I can then connect to the ADC clock input.

---

So I must assume that you generate the "ADC clock output" inside the FPGA and you want to drive it out to the ADC using a pin that just happens to connect to one of the SMA connectors? See my paragraph above.

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Could you please explain what the output swing and logic swing means? When I refer to the schematic for the board I can only access single-ended pins that are connected to banks at voltages of 2.5V and 3.3V but the ADC clock input doubles the input voltage and the ADC chip datasheet says that the maximum voltage for the clock is 3.5V.

[eteam00]

When I connected my clock signal to one of the two SMA clock outputs I got an error

So let's not do that.  What is the clock frequency you intend to use?

I need to output my clock so that it will also be the clock for the ADC I'm working with.

This is called "clock forwarding", when you use an ODDR2 block to copy an internal clock signal to an FPGA output pin (or pins).

"Tied to a clock" means in VHDL the clock will be connected a top-level output and then in the constraints file it will be connected to a single-ended pin that I can then connect to the ADC clock input.

Please provide a link to the datasheet of the ADC you are using.  This will save us some time and several posts.

Could you please explain what the output swing and logic swing means?

This refers to the nominal analogue voltage levels of digital signals on a circuit board when logic '0' (usually - but not always - GND) and when logic '1'.  This is a crude description, for expedient purposes in this post.

When I refer to the schematic for the board I can only access single-ended pins that are connected to banks at voltages of 2.5V and 3.3V

As mentioned in a previous post, you can define (in your design) pairs of single-ended signals (with restrictions) to be differential signals.  I believe the board design supports this use.  So you are not constrained to single-ended signals between the FPGA and external devices.

but the ADC clock input doubles the input voltage and the ADC chip datasheet says that the maximum voltage for the clock is 3.5V.

It is the ADC evaluation board which you are using -- not the ADC itself -- which doubles the clock input voltage with a transformer.

-- Bob Elkind

[cosmiac]

Here is the ADC User Guide:

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slau194&fileType=pdf

Here is the ADC Chip Datasheet:

http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slau194&fileType=pdf

On page 3 of the Datasheet is where I found the max voltage rating for the clock input (3.5V) and page 7 of the User guide is where it says the clock input is stepped up by a factor of two. Please let me know if I am interpretting this information incorrectly.

I just have never heard it refered to as "swing voltage" before. Right now I'm running my clock at 100MHz but eventually I want this at 400MHz. I got the ODDR2 working fine for one of the ALI connector pins but the swing voltage for that is 3.3V so I didn't want to risk connecting it to my ADC since it would be way above the 3.5V max for the chip once doubled.

Thank you all for your help, right now I am using a signal generator to clock the ADC, but since this is not sychronized with the ADC clock I will get less accurate data so I would really like to figure out how to sync them via the methods we are discussing if possible.

[eteam00]

You posted the link to the Evaluation Module (board) User Guide twice.  Are you using the ADS5474 ADC?

-- Bob Elkind

[cosmiac]

Sorry about that! It's the ADS54RF63
http://www.ti.com/lit/ds/symlink/ads5463.pdf

[eteam00 · Accepted solution]

On page 3 of the Datasheet is where I found the max voltage rating for the clock input (3.5V) and page 7 of the User guide is where it says the clock input is stepped up by a factor of two. Please let me know if I am interpretting this information incorrectly.

What you call a datasheet is actually the user's guide for the evaluation module.  The ADC (a component, not a circuit board) does not provide a voltage doubler, and our different uses of the term 'datasheet' resulted in confusion.

You are right to be concerned.  If you want to source the ADC clock from the FPGA, you will need to reduce the output swing to accommodate the evaluation module.  A simple method would be to replace 0-ohm resistor R23 on the eval module with a 49.9 (or higher) ohm resistor.  This will effectively reduce clock signal amplitude by 50% (or more).

-- Bob Elkind

[cosmiac]

Ok thanks!