Spartan® Family FPGAs

[sridar]

I inferred single port BRAM for the size of 27*65 using two methods, RTL and coregen.

Using coregen infers 1 RAMB16 block and RTL logic of same infers 2 RAMB16 blocks. I use spartan-3e FPGA.

What is the reason for this??

[eilert]

Hi Sridar,

some time ago I made the same observation as you did now.

The coding rules for infering BRAMS are very tight, and sometimes not really clever.

So, unless you haven't made some mistake in your code (hard to say without anything posted) the synthesis tool has a different oppinion than you about how to interpret it.

Best way to clear this is to open a webcase and send your code and the coregen results of your intended result to XILINX and hope for improvements.

Have a nice synthesis

  Eilert

[sridar]

Thanks Mr.Eilert,

I just followed the guidelines from xilinx guides to infer a RAM. I wil file a case against this.

One more think i noticed is, number of RAM blocks inferred for dual port is two times greater than single port through coregen for the same memory size. Is this correct?

Thanks again and i have attached my code for single port RAM below.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity memory is

    port (
    addr: IN std_logic_VECTOR(4 downto 0);
    clk,din,en,we : IN std_logic;

    din : in std_logic_vector (64 downto 0);
    dout: OUT std_logic_VECTOR(64 downto 0));
  

end memory;

architecture Behavioral of memory is

Type memd is array  (0 to 26) of std_logic_vector (64 downto 0);
signal memor : memd;


begin


process (Clk)
begin
   if (clk'event and clk = '1') then
      if (en= '1') then
         if (we = '1') then
           memor(conv_integer(addr)) <= din;
         else
            dout <= memor(conv_integer(addr));
         end if;
      end if;
   end if;
end process;

end Behavioral;

Message Edited by sridar on 08-14-2009 02:09 AM

Message Edited by sridar on 08-14-2009 02:23 AM

[prashant_unch]

Hi,

As per your code , u r reading synchronously.

If you read independent of clock ,tool may infer BRAM.

Just check it.

[bassman59]

Hi --

process (Clk)
begin
   if (clk'event and clk = '1') then
      if (en= '1') then
         if (we = '1') then
           memor(conv_integer(addr)) <= din;
         else
            dout <= memor(conv_integer(addr));
         end if;
      end if;
   end if;
end process;

I wonder if the "else" which does your read is the problem. Single-port BRAM read is independent of writes (although of course they share the same address). Your code blocks the read during writes, and I wonder if the synthesis tools think you want something else.

Try this:

mybram : process (Clk)
begin
   if rising_edge(clk) then
      isEnabled : if (en = '1') then
         isWrite : if (we = '1') then
           memor(conv_integer(addr)) <= din;

         endif isWrite:;

         dout <= memor(conv_integer(addr));
      end if isEnabled;
   end if;
end process mybram;

[sridar]

As per my knowledge, tool infers DRAM if read asynchronously (This is all xilinx guides say).

[sridar]

 >> Your code blocks the read during writes, and I wonder if the synthesis tools think you want something else.

The problem is that the code infers BRAM, but only the number of BRAMs are different when using RTL and coregen.

And i tried the code snippet, still the same result.