Spartan® Family FPGAs

[dterhaar]

In our own design 3 AD9252 ADC's are connected to bank0 by means of lvds. It is a spartan 6 XC6SLX150FGG484. One AD9252 contains 8 ADC's so you have 24 lvds serial channels in 3 clock domains. These are deserialized in FPGA fabric. Speed is maximal 20MS/sec. It works fine.

Because we are doiing a redesign, we are checking the pin planning in our current design whether it is able for deserialization with ISERDES2. Perhaps this might be advantageous in the future.

We saw that there are 8 BUFIO2 clock regions. One for each half side of the device. These regions are TL/TR/RT/RB/BL/BR/LT/LB. This is shown in guide ug382 (spartan 6 clocking) figure 1-6.

See also xapp1064.pd: case2/figure2 deserialization with BUFIO2 primitives.

UG385, "Spartan-6 PCB design and Pin planning guide" would list the pins for these BUFIO2 clocking regions but I couldn't find the table (if there is one).

In our design, bank 0 is used. I want to know which pin pairs IO-LxxN_0/IO-LxxP_0 is TL (top left) and which is TR (top right).

Can someone help me where I can find this information?



[eteam00]

See UG385, Table 2-9.  The information you seek is very clearly displayed.

-- Bob Elkind