Spartan® Family FPGAs

[adam123]

I'm using a Spartan-6 PLL to remove clock jitter, and I have a lot of flexibility in what I set the VCO frequency to (by manipulating the M+D values as well as the parameters on the DCM feeding the PLL).

UG382, page 102, says "the goal is to make D and M values as small as possible while keeping f_VCO as high as possible" which seems to imply that the PLL performs best when the VCO frequency is as high as possible yet still within the datasheet parameters -- around 1Ghz.  Is this true?  I'm not an analog guy, but all things being equal I'd suspect that circuits don't generally perform best at the outer limits of their specifications.

If it matters, I am using the PLL only for jitter filtering.

[jheslip · Accepted solution]

The higher the VCO frequency then usually the less jitter is seen on the output so if you can keep the VCO at the top of its allowed range.

[adam123]

Thanks jheslip, that was really helpful!

[juergenatduerr]

I do not know about the internal structures of the Xilinx PLLs, but usually, PLLs running on higher freqs have a relatively shorter feedback loop, if you take the subsequent clock division into account.