Spartan® Family FPGAs

[eteam00]

Unfortunately this is an existing system and I'm trying to use what is available. The generated clock has 2 phases divide by N and divide by N+1. Long term you get the correct number of edges. I'm hoping the PLL will smooth the clock out enough to make it useful. (I understand about the jitter all the PLL does is smear it out)

I do not fully understand what you have in mind, but what you have said so far does not sound promising or encouraging.

The current configuration has the VCO at 250MHz and compare at 25MHz with the output clock as ~25MHz. The output is further divided externally before used.

For Spartan-6, 250MHz is too low for PLL VCO frequency.  Check the datasheet on this (DS162), Table 52.

Currently the generated clock is derived for a 250MHz clock and now that I have started fixing the BUFGs etc. I am hoping to used 500MHz as the source to get the jitter to a smaller initial value.

This (500MHz)  is only possible from an external input via a GCLK pin, in case you were wondering.

The only practical requirement for low-jitter audio clock is for conversion to analogue.  The DAC clock should not *ever* be sourced from the FPGA if you care about minimum possible distortion (which is an artifact of clock jitter).  Do not confuse the clock for transferring data from FPGA to DAC with the conversion clock.

-- Bob Elkind

[eteam00]

I have submitted webcase 927109.  The initial notes are as follows:

There is an apparent contradiction about clock sources to PLLs and DCMs.

Figure 3-1 includes "General Interconnect" as a selectable PLL or DCM clock input source.

On page 106, PLL Clock Input Signal sources are summarised, and "general interconnect" is not one of the available options.

As the number of clock buffers on Spartan-6 devices is quite limited, the availability of sourcing PLL or DCM inputs from general interconnect (without using one of the precious clock buffers) can determine whether or not a design is suitable for Spartan-6 devices.

Webcase 927109 is now closed.

UG382 Figure 3-1 should show "General Interconnect" as a selectable clock input source for DCMs, but not PLLs.

UG382 Table 2-2 should be updated to show "General Interconnect" as a selectable clock input source for DCMs.

A CR has been submitted.

In sum:  Spartan-6 DCM can accept input from general fabric logic signal, but Spartan-6 PLL cannot.

-- Bob Elkind