Spartan® Family FPGAs

[eteam00]

My question was academic and related to setup time.  Would the register a ever be zero when CLK is 1.  If so then the setup idea doesn't hold water.

I'm just trying to nail down these concepts.

Cool!  Another anally-retentive mind-controlling string-pulling teaching opportunity!

Here is a more practical diagram to illustrate what you describe as a "concept":

                                                       register

                                                    +------------+

                       +--------------+          C1 |            |

                  +--->| path delay D |------------>| D input    |

               C0 |    +--------------+             |          Q |----> reg output

clock input >-----+                                 |            |

                  |    +--------------+             |            |

                  +--->| path delay C |------------>|> CLK input |

                       +--------------+          C2 |            |                                                                          +------------+

The two different path delays from clock input to the register are not identical.

• Case 1: If path delay D is much longer than path delay C, then the register output will always be '0'.
  
• Case 2: If path delay D is much shorter than path delay C, then the register output will always be '1'.
• Case 3: At some point between Case 1 and Case 2, the register output will vary randomly.
  

 Does this make sense, my dear mind-controlled puppet ?

(just trying to lighten things up, don't take this personally -- I didn't)

If this doesn't make sense, it would probably help if you draw waveform timing diagrams for each of the three cases described above, including points C0, C1, and C2 in each diagram.  The important consideration is the state of signal C1 at the time of the rising edge of signal C2.

In my first posting I said "I've thought about using opto-couplers..."

The electrical interface question is orthogonal to the signal timing issue, as rcingham has mentioned in post #13 in this thread.

-- Bob Elkind

[mow2000]

Thanks bob,  you might have finally broken through to my pea brain.  And i appreciate the time it must have taken to draw that ascii circuit.  Nicely done.

[eteam00]

You are welcome.

-- Bob Elkind

[gszakacs]

Oddly enough it is coded to receive data on the rising edge of the clock.  It doesn't seem like it should but I have verified it on the scope.  That's why the 1 case comes before the 0 case.  Originally it was 0 then 1 but the data was changing on the negative edge of the clock - so I reversed the numbers.  Something must be getting inverted somewhere...

 Synchronous hardware processes are systolic.  Here's the simplest way I can explain that:

1) The process triggers at a clock edge.

2) All of the process inputs are sampled (everything on the right side of the process assignments)

3) All of the process outputs are calculated using the sampled inputs.

4) All of the process outputs are updated to the new calculated values.

Note that specifically this means that step 4 - updating outputs, happens after all of the

assignments are made.  So the order of the assignments within the process only matters

if there is more than one assignment made to the same output.  Otherwise:

clk1out <= ~clk1out;

if (clk1out == 1) . . .

is the same as:

if (clk == 1). . .

clk1out <= ~clk1out;

So in fact nothing is "getting inverted."  In your case statement, the 0: clause will

happen when clk1out was zero before the clock edge, and because on every clock

edge you invert clk1out, this means clk1out will be one after the edge.  This rising

edge of clk1out will happen at the same time as any assignments made in the 0:

case.  What you see on the scope is that data1out will take on the value of data1

exactly coincident with the rising clock edge.

-- Gabor

[bassman59]

---

mow2000 wrote:

My question was academic and related to setup time.  Would the register a ever be zero when CLK is 1.  If so then the setup idea doesn't hold water.

---

The level of the clock is not relevant. It's the active edge that matters. Digital hardware 101: on the rising (or falling, if applicable) edge of the clock, the input is transferred to the output. At all other times, the input is not interesting and can change however it wants.

Digital hardare 101, day 2: the input to the flip-flop must be stable (unchanging) during the "setup" time before the edge of the clock, and must remain stable during the "hold" time after the clock. If either of those two requirements aren't met, the result is undetermined.