Spartan® Family FPGAs

[matrix39]

dear all

i want to know that do we need only parallel termination when interfacing DDR SDRAM (using SSTL2) with spartan-6 or series termination also as i have seen in spartan3E and spartan3 PCIe starter kits. this is confusing from the documents...

secondly can the internal termination features of the spartan-6 are helpful in this regard or not !! If yes HOW ??

i have read the thread posted by KIRAN and long discussion there but still can figure out that planahead is a way to estimate for SSN or .........how does it help calculate termination values or recommended scheme also.. which I/O standard is better in my case.

moreover can i generate 2.5V from a regulator and generate VTT using a simple voltage divider circuit for Vref and terminator resistors.

best regards

matrix

[eteam00]

i want to know that do we need only parallel termination when interfacing DDR SDRAM (using SSTL2) with spartan-6 or series termination...

My opinions:

• Bidirectional DQ, DQM, and DQS (strobe) lines:  on-die termination
• Differential clock:  parallel termination.
• Address/control groups:  either parallel or series termination

This advice applies specifically to Spartan-6 MIG/MCB designs, because Spartan-6 MCB does not support more than a single memory device, and all interface signals are (by construction) 2-pin point-to-point signal lines.

Your mileage may vary, no guarantees, and analogue circuit simulation is your responsibility. (not bad for someone with no formal legal training!)

-- Bob Elkind

[gszakacs]

It's not clear what you mean about "on-die termination" which usually refers to the memory end of the net.

I was not aware of ODT on DDR (original not DDR2) parts. The 2.5V SSTL2 seems to imply the older

generation memories.

Unless you have some other pressing need to use "original" DDR SDRAM, I would suggest using a

newer family (DDR2 or DDR3) which will save power while allowing higher transfer rates.  If your

reasoning is to use the remainder of the bank for other 2.5V I/O, then I'd look at whether you could

change the IO standards for those few remaining pins to work at 1.8V or lower Vcco.

-- Gabor

[eschabor]

I've interfaced a Spartan 6 to DDR SDRAM before, take a look at my schematic and UCF file:

http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/48

The approach I took mainly uses the Spartan 6 built in termination, with just 3 external resistors at the DRAM end of the clock and DQS signals.

Bob wrote:

> My opinions:

> Bidirectional DQ, DQM, and DQS (strobe) lines:  on-die termination
> Differential clock:  parallel termination.

> Address/control groups:  either parallel or series termination

The scheme I used is:

                               FPGA end                                                DRAM end

DQ,DQM:              series and parallel                               none

DQS:                     series and parallel                                parallel (using discrete resistors)

diff clock:              none                                                          parallel (using discrete resistor)

Addr/control:        series                                                       none

All of the FPGA end termination uses Spartan 6 internal untuned termination.

> moreover can i generate 2.5V from a regulator and generate VTT using a simple voltage divider circuit for Vref

> and terminator resistors.

Don't do that!  You need much better load regulation than a voltage divider provides, especially for VTT.

A TI TPS51100 does it well, or use a RichTek RT9026 if you want a cheaper alternative.

Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
Spartan 6 LX75 with 2GB DDR3 DIMM for $375:
http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56

[eteam00]

It's not clear what you mean about "on-die termination" which usually refers to the memory end of the net.

I was not aware of ODT on DDR (original not DDR2) parts. The 2.5V SSTL2 seems to imply the older

generation memories.

Thank you , Gabor.  You are correct.  Please ignore my previous post.

-- Bob Elkind

[matrix39]

Dear stephen

thanks a lot for your valuable suggestions and recommmendations and reference schematic... just for information if i had used spartan-3 then should i have used the external parallel and series termination for the DQ & DQS and parallel termination for the address lines as io saw in SP3 PCIe starter schematic ....

secondly i have changed my mind to use the DDR2 SDRAM with SP6 due to availability in stock fortunately, i was unaware of earlier.

So what i conclude now that i need only 50 Ohm parallel termination (external) on the address, RAS,CAS and WE pins only as seen in some schematics. DQ/DQS will be terminated internally in FPGA in a parallel fashion (i guess). BUT WHY then a Micron document ("H/W tips for point to point system design", TN4614, page 11) says that parallel termination is only required  when at least one of the following is true

1. five or more DDR devices

2. >2in trace lengths

3. poor simulation results

4. single or multibit error during prototyping (after simulation)

What if none of the above is true Should i go for series termination by hit and trial as explained on page 10 of the same micron document.

Moreover which tool should i use for simulation of the FPGA and DDR/DDR/DDR3 interface...is there any available free of cost ??

best regards

matrix

[eteam00]

I did not read (or re-read) the Micron TNR doc, but you might easily paraphrase your summary as follows:

You don't need to use parallel termination unless the alternatives do not work.

or, more succinctly...

You don't need to use parallel termination unless you need to use parallel termination.

Just to be clear:  the list of four reasons to consider using parallel termination may or may not have anything to do with parallel termination.  Let's take these one by one ...

1. five or more DDR devices

If all five (or more) devices are located very close to each other, there may not be a problem using series termination.  But usually more load pins means that some load pins are more distant from the trace endpoint, and signal settling time will suffer as a result.

For clock signals (any signal which is edge-active), you should not consider using series termination for lines with more than a single load pin.

2. >2in trace lengths

With a single load pin, trace length should not matter for a properly designed series-terminated signal line.  This is done every day with utterly reliable results.

3. poor simulation results

There are plenty of ways to poorly design a signal trace, with or without parallel termination.  Having said that, circuit simulation results can be used to suggest that parallel termination will work better for your design -- usually because of some aspect of your design is unsuitable for series termination.

4. single or multibit error during prototyping (after simulation)

Same answer as #3 applies here:  there are plenty of ways to poorly design a signal trace, with or without parallel termination.  The point of #4 is that you can skip the time, trouble, and expense of circuit simulation and find that your design is unreliable simply by building the board and testing it.

Just to clarify:  In practice there is no such thing as non-terminated signal lines.  The output driver itself has a non-zero output impedance which contributes series termination to the signal line it is driving.  So "unterminated" line is a form of series termination.  Depending on specific details, the driver's impedance may be a good enough match for a reliable series-termination solution.  The extent to which the driver's impedance is not a good match will contribute to increased ringing or settling time.

Have you read this thread?  It might be helpful to you...

Next question:  Why choose DDR2 over DDR3?  If this is a production-intent design, DDR2 is likely to become more expensive and less available than DDR3 devices in the near future.  The crossover point for DDR2 to DDR3 was reached several years ago.

-- Bob Elkind

[matrix39]

thanks a lot, bob.

this is a development board actually and i want to experience DDR2 as we have never used it before and may be used in upcoming boards. i am using only one IS43DR16640A-3DBL (DDR2, 64M X 16) with spartan-6 MCB bank3. so what i am planning now to have parallel resistors (for safer design) on the address lines and "0" ohm series resistors on the data and strobe lines to replace them with optimal ones (if in case i need them).

apparently what i figure out in this specific case is that i can use internal FPGA termination for data/strobe lines and connect address lines with out any series/parallel resistors (for a single chip located near the FPGA).

moreover i have 100/96MHz and a differntial 200MHz crystal on my board and plan to use it at 333MHz to 400 MHz. what i understand uptil now that FPGA will generate proper clock if a design is created using MIG and implemented thru MCB.

how can i use IBIS models to simulate my scenario.

best regards

matrix

[eschabor · Accepted solution]

just for information if i had used spartan-3 then should i have used the external parallel and series termination for the DQ & DQS and parallel termination for the address lines as io saw in SP3 PCIe starter schematic ....

For Spartan 3 to a single DDR1 (ie point to point) I recommend:

Signal                      FPGA end                                  DRAM end

DQ,DQS,DM           external series and parallel   external series and parallel

A,BA,control            external series                          external parallel

Assuming 50 ohm traces the series resistors should be 25 ohms and the parallel resistors 50 ohms (to VTT).

That setup will work, even for quite long traces.  If the traces can be made shorter then the need for the termination resistors reduces - the series resistors can safely be reduced in value and the parallel resistors can safely be increased in value.  In the case where the traces are extremely short the series parallel resistors can be increased to infinity (not loaded) and the series resistors can be reduced to zero (shorted out). "extremely short" in this case means: "much less than one third of the distance the wave can travel in its rise or fall time" eg for a signal with 400 ps rise and fall times travelling along a trace at 150mm per ns "extremely short" means much less than 20mm, so I predict 10mm would be fine without termination.

secondly i have changed my mind to use the DDR2 SDRAM with SP6 due to availability in stock fortunately, i was unaware of earlier.

DDR2 have On Die Termination for the data lines, which makes termination easier.

As Bob has pointed out though, why not use DDR3 ?  They are available at an almost reasonable price:

http://www.digikey.com/product-detail/en/W631GG6KB-15/W631GG6KB-15-ND/3124559

So what i conclude now that i need only 50 Ohm parallel termination (external) on the address, RAS,CAS and WE pins only as seen in some schematics. DQ/DQS will be terminated internally in FPGA in a parallel fashion (i guess).

For Spartan 6 to a single DDR2 or DDR3 (ie point to point) I recommend:

Signal                      FPGA end                                  DRAM end

DQ,DQS,DM           internal series and parallel   internal series and parallel

A,BA,control            internal series                          none

If you don't care about power dissipation the parallel resistors should be the same as the trace impedance (safest for SI), if power matters then the parallel resistors can be increased as long as the trace length is short and/or the series resistors are increased.

Default series resistors values are:

SSTL2 (2V5,DDR): 25 ohms

SSTL18 (1V8,DDR2): 20 ohms

SSTL15 (1V5,DDR3): 34 ohms

These values can be increased up to around the trace impedance if the parallel termination is weakened or dispensed with.

For my most recent S6 DDR3 project I set up the DDR3 for 40 ohms series resistance and 40 ohms parallel resistance and the S6 for 25 ohms series resistance and 75 ohms parallel resistance.  The transmission lines used are 40 ohms.

Full details of my S6 termination settings can be seen from the UCF file here:

http://www.sioi.com.au/shop/product_info.php/cPath/24/products_id/56

Moreover which tool should i use for simulation of the FPGA and DDR/DDR/DDR3 interface...is there any available free of cost ??

A popular commercial tool is HyperLynx, which is expensive.  

A free tool that can still be very useful is Spice.  You can model this type of signalling quite well using transient simulation of transmission lines in Spice.

Best regards,

Stephen