06-30-2009 07:05 AM
Just how big is the memory controler / ddr ( 1 2 or 3 ) continous bandwidth.
I see notes of around 800 Mega Bit per second, is this true?
seems low for a DDRx running at 120 plus MHz clock, double data rate, and 32 plus bits wide ?
thats something like a one clock in 12 carries data.
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06-30-2009 08:28 AM
When you see reference to something like "800Mbps DDR2" - they are saying that the clock is 400MHz and each bit is tranferring data on both edges of the clock.
The bandwidth capability will be the bus width multiplied by the bus width.
The effective bandwidth can be much lower and is impacted by the controller algorithms (e.g. we use a Least Recently Used algorithm on Virtex-5 that can keep multiple banks open and improves the internal latency), access pattern, direction, burst length, refresh considerations, etc.
You'll see other features on the V6 controller to furher increase effective bandwidth.
06-30-2009 09:19 AM
Agree with you in that performance is situation related, and it's double data rate, but quoting from the spartan 6 product brief.
"integrated Memory Controllers Only low-cost FPGA with integrated memory controller blocks
So is that 800 Mega bits per second with a 128 bit interface, i.e. an average clock speed of around 3 MHz on each pin,
is that not very slow for a memory that has a clock of 400 plus MHz, and data is double data rate ?
06-30-2009 09:28 AM
3MHz on each pin would indeed be very slow. But there appears to be some confusion on the internal and external interfaces.
The S6 MCB offers an external interface of 4, 8, or 16-bits. That is where the 12.8Gbps peak bandwidth is coming from.
Internally, you have to run the fabric back-end at a slower and wider single-data rate interface to handle the data inside the FPGA. The backend of the MCB is a 32, 64, or 128-bit data bus inside the FPGA.
More details on in the MCB User Guide:
06-30-2009 09:54 AM
thank you timpe,
yep, the web link you quote is where I got the info I quote to you from.
Yep agree, inside the FPGA we run single data rate, not DDR, and we run wide to account for the slower data rate inside the FPGA compared to the out side.
but your not answering question here, is the guaranteed continuous data rate of the Xilinx interface as stated only around 3 MHz per pin ?
this can't be, can it ?
Simplify question, specific, not general.
What sustained data rate can I get into or out of a DDR 3 memory, using the fastest Spartan 6 built in memory controler, double chanel, using the fastest DDR 3 chips I could get.
06-30-2009 11:29 AM - edited 06-30-2009 11:29 AM
It isn't clear to me where you keep getting this "3MHz per pin" The only pins are the external interface and they can transfer up to 800Mbps each. So for a 16-bit interface, that would be a peak bandwidth of 12.8Gbps for the entire MCB. The back-end interface will be running slower, wider, and SDR.
I don't have the final characterization #s available. But the preliminary numbers I'v'e seen show very good effective utilization when you consider sustained throughput. It obviously depends on the type of memory (e.g. DDR2, DDR3, or LPDDR), the type of transfers, direction, etc. For example, the efficiency drops with random addressing and shorter burst patterns. These numbers are not official but for DDR3 I see a range of:
best case: high (95%+) for burst writes, length 32
down to: around 50% with random operations with a burst length between 4 and 16
There are obviously a range of operations in between here.
Even at 50% efficiency, you still have 6.4Gbps of effective banwidth.
Where are you getting this 3MHz per pin?
06-30-2009 12:00 PM
to quote the product brief.
" Integrated Memory Controllers Only low-cost FPGA with integrated memory controller blocks
so to be clear, you are saying the 800 Mega bit per second quoted in the Spartan 6 product brief is the maximum peak data rate per external pin of the Spartan 6 ?
06-30-2009 12:20 PM
Yes. 800Mbps * 16 = 12.8Gbps
Obviously the narrower configuration of x8 or x4 will half or quarter the respective maximum bandwidth.
And there are some considerations as I outlined above for real world performance.
I believe this convention is fairly standard (bitrate per pin) in the memory industry.
It is clear from the moderation on my previous posts you didn't like something I said... I said "each bit" from the beginnning. I apologize if this was not more obvious
06-30-2009 12:40 PM
06-30-2009 01:39 PM
We have deviated a long way from the original simple one line question.
but to go back to my original question,
"Just how big is the memory controller / ddr ( 1 2 or 3 ) continuous bandwidth"
To clarify, I'll restate it slightly.
" the spartan 6 has a dedicated memory controller. Using the fastest spartan 6, and the fastest DDR3 memory the controller supports, does Xilinx have any numbers as to what continuous read or write performance can be expected .
A hypothetical example to clarify things. If I have a continous data generator inside the spartan 6 of say 128 bits wide, at 200 MHz. This data generator can not be stopped, it must free run at the 200 MHz. Can this data be constantly written to the DDR 3 by the memory controler inside the spartan 6, does the controler have sufficient buffering to take care of the times when the controler is performing it's house keeping ? "