Spartan® Family FPGAs

[baesae]

Hey there

I do have some questions regarding multiplication on Spartan 3 FPGAs. Spartan 3 contains up to 104 dedicated multipliers. Apparently I can chose to pipeline these multipliers (I. e. the 'Complex Multiplication 3.1' block of System Generator offers me this opportunity, furthermore the datasheet of the mentioned block contains tables relating the speed of the multiplication and the amount of pipelining-stages).

I made some tests to see the relation between pipelining stages and speed using a 17x17bit signal on the 18x18bit multiplier to find the optimal amount of stages for my design. The result was strange. In the synthesis report the worst case path time decreased with increasing amount of stages (what sounds logical to me), meanwhile the timing report displayed worst case paths of unreasonable 1-2ns for the 0 piped-multiplication and reasonable 10-15ns for 1 or 2 stages pipelining. but still, applying more pipes did not help to increase speed, contrariwise the speed decreased with more stages.. (all this applying the same port map and ucf-file for generation-process)

Now my questions

a) are dedicated multipliers designed to be piped or is this option rather for the LUT based multiplication architecture? This would at least explain why enhancing grade of pipelining does not enhance speed when using dedicated multipliers.

b) The nicest solution would be to let System Generator chose the amount of stages by itself. Problem here is I cannot see how many stages were inserted. Thus I cannot delay the paths parallel to the multipliers for the appropriate time. Where can I see how many stages were used?

btw. I'm using ISE 13.4 and Matlab 2012a

Regards

baesae

[rcingham]

Synthesis Timing Reports are unreliable.

Only the Post-PAR Timing Report is reliable.

[baesae]

Thanks for your answer. Sorry, wasn't very clear there. By "timing report" I ment the Post-PAR Timing Report I opened after PAR in 'Design-Summary -> Post-PAR Static Timing'

Apparently for a zero delay dedicated multiplication, the synthesizer removes the whole component (otherwise 1-2ns worst case paths reported by 'Post-PAR Timing Report' are not possible..). I ask myself: Why should the synthesizer remove the component with zero delay, but not with 1 or 2 delays/pipes, eventhough the environment stays the same.

And most important: where can I find the number of pipe stages in System Generator when I let System Generator select the ideal number of pipes? :)

[rcingham]

Never used System Generator.

Hopefully, someone else can help you, but the experts for that tool tend to lurk in the 'DSP Tools' forum.