Spartan® Family FPGAs

[eteam00]

@ccon,

If you check the source code in post #1, you will notice that your suggested clock doubler is completely unnecessary.  The "double edge" clock is, in fact, bit[26] of a clock divider counter.

-- Bob Elkind

[ccon67]

---

eteam00 wrote:

@ccon,

If you check the source code in post #1, you will notice that your suggested clock doubler is completely unnecessary.  The "double edge" clock is, in fact, bit[26] of a clock divider counter.

-- Bob Elkind

---

Oh, I didn't read his code for the counter..., in my previous post I'd better use the name 'dual dege' instead 'double edge'  :-)

Anyway, If we use the frequency doubler approach (actually it converts any edge to a pulse) we need to change the counter to a true synchronous counter .. .

Again, synchronous design will make our lives easier... isn't it

[eteam00]

Anyway, If we use the frequency doubler approach (actually it converts any edge to a pulse) we need to change the counter to a true synchronous counter .. .

The counter div looks like a "true synchronous counter" to me.  Have another cup of coffee, and look again. :)

-- Bob Elkind

[ccon67]

I haven't read to code yet.. I have trouble to read others codes, even the best ...but mine :-)

Anyway, It appears the OP is good enough in Velilog... he will know where to insert the freq doubler...won't he ?

[ccon67]

My original suggestion is this:

1) Convert the dual edge to traditional single edge clock

2) Use the single edge clock as ... the single edge clock

--- yes and thanks for the tips :Look before you post

:-))))))))))))))

[eteam00]

I haven't read to code yet.. I have trouble to read others codes, even the best ...but mine :-)

This makes it all the more difficult to make useful comments and suggestions, I would think.  It's very brave of you to try to help this person with a problem, without understanding the code being discussed or reviewed.

It might be helpful, in the future, to preface your well-intended suggestions with a disclaimer.  Example:

I did not read or review your source code, but perhaps this suggestion may nonetheless be useful to you...

-- Bob Elkind

[ccon67]

When suggest him to another aproach, it may not necessary to read the code in details, does this make any sense to you ?

Now I see why you have thousand of distribute in this board... so fun to stick around and bitching any small of this and  that

do you have another job ?

[eteam00]

When suggest him to another aproach, it may not necessary to read the code in details, does this make any sense to you ?

Of course this makes sense.  In this case, however, your clock doubler suggestion is a bit of a distraction to an inexperienced designer looking for clear and simple direction.

A number of times -- in these forums -- I have tried to make useful suggestions without properly reviewing the code (or reviewing the simulations results or using the same IP core, etc.).  When this occurs, I usually preface my comments with a suitable 'have not read your code' (or similar) disclaimer, so that everyone knows that my comments do not reflect an understanding of the code.

In particular, I hesitate to comment on VHDL code because my VHDL skills are weak -- very weak.  In such cases, it usually serves the designer seeking help if someone more knowledgeable provides assistance.

-- Bob Elkind

[ccon67]

---

eteam00 wrote:

When suggest him to another aproach, it may not necessary to read the code in details, does this make any sense to you ?

Of course this makes sense.  In this case, however, your suggestion is a bit of a distraction to an inexperienced designer looking for clear and simple direction.

-- Bob Elkind

---

Well, distraction is what you think... I have no idea how and what level of the OP..  He could be better than you and me... in design and knowledge, just this problem he may stuck with...

We need to exchange several posts to see how/what going on then move to the next step of suggestion...

It appear that you under- estimate everyone else knowledge- but yourself

[bassman59]

---

ftwilliam wrote:

I am implementing a dual-edge-register within the module "dualedgeregister", by making use of 2 FF; where one use a positive edge clock, and the other use a negative edge clock; hence the module "dualedgeregister" capture input on both edge of the clock.

---

if the inputs to this double-edge flip-flop come from outside the FPGA, then you can put them into the IOB and use the IDDR2 flip-flop, which does what you want. Note that the output of the IDDR (inside the FPGA) has two bits, one for the bit on the rising edge of the clock and the other for the falling edge.

If it's inside the FPGA, then you're stuck because the fabric doesn't have a flip-flop that can be clocked on both edges. But you can fake it by doubling the clock frequency with a DCM and using the doubled clock and an odd/even bit that toggles every tick of the doubled clock to sort out whatever it is you're trying to do (which I haven't been able to figure out).