Spartan® Family FPGAs

[0989]

Hello I have a testing sinusoidal wave that goes into an ADC and into the Expansion Connector. Everything is fine, except when i want to have a trigger that only lets the signal get recorded when a Go signal is 1.

This is my code: (din is the data input)

process(clk,state,din)
begin
if Reset = '1' then
Go <= '0';
elsif rising_edge(clk) then
if State = '1' and din > "10000011" then
Go <= '1';
end if;

end if;
end process;

Am I making this too simple? Without the din>"10000011"  the code works, of course.

Thank is advance

[gszakacs]

You didn't say exactly what doesn't work.  Do you mean that Go never gets asserted?

In your clocked process, only clk should be in the sensitivity list.  This won't affect synthesis

but it ensures that synthesis matches simulation.

Have you simulated the design to see if there is an obvious reason why it fails?

How did you define din?  Are you sure that it becomes greater than "10000011"?  For example

if din was 8 bits signed, then it could not possibly become greater than this unsigned value.

Also the magnitude comparison will depend on the libraries you are using (no offense Bassman, but

this is why I always use Verilog).

I also noticed that once asserted, Go will stay asserted until you re-assert Reset.  Is this intentional?

-- Gabor

[0989]

Turns out the problem was on the top design file. Sorry. This code actually works. I'll optimize the sensitivity list as stated. Thank you for your interest.