Spartan® Family FPGAs

[jembeng]

I designed a board using XA6SLX45 (automotive) and M25P64.

I could download bit file, but I couldn't program SPI flash.

Message is below

=============================================================

INFO:iMPACT - Current time: 2012-04-22 &&&& PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 25000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file C:/Xilinx/13.4/ISE_DS/ISE/spartan6/data/xc6slx45_spi.cor.
'1': Downloading core...
 LCK_cycle = NoWait.
LCK cycle: NoWait
done.
'1': Reading status register contents...
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0010 0100 1100 1100
INFO:iMPACT:2492 - '1': Completed downloading core to device.
INFO:iMPACT - '1': Flash was not programmed successfully.
PROGRESS_END - End Operation.

=============================================================

Status register is below

=============================================================

'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[2] RESERVED                                                               :         0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR                                  :         0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR                                  :         0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                      :         0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED                       :         0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED                 :         0
[8] RESERVED                                                               :         0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR                                  :         0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR                                 :         0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR                     :         0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS                       :         0
'1': Reading status register contents...
[0] CRC ERROR                                                              :         0
[1] IDCODE ERROR                                                           :         0
[2] DCM LOCK STATUS                                                        :         1
[3] GTS_CFG_B STATUS                                                       :         0
[4] GWE STATUS                                                             :         0
[5] GHIGH STATUS                                                           :         1
[6] DECRYPTION ERROR                                                       :         0
[7] DECRYPTOR ENABLE                                                       :         0
[8] HSWAPEN PIN                                                            :         1
[9] MODE PIN M[0]                                                          :         1
[10] MODE PIN M[1]                                                         :         0
[11] RESERVED                                                              :         0
[12] INIT_B PIN                                                            :         1
[13] DONE PIN                                                              :         1
[14] SUSPEND STATUS                                                        :         0
[15] FALLBACK STATUS                                                       :         0

=============================================================

GTS_CFG_B STATUS = '0' and GWE STATUS = '0'

==> It seems that FPGA couldn't start-up after downloading 'xc6slx45_spi.cor'

I also designed a similar board using XC6SLX45.

In this board, there is not any problem in programming SPI flash

Is it difference programming flash between XA series and XC series ?

[eteam00]

==> It seems that FPGA couldn't start-up after downloading 'xc6slx45_spi.cor'

If DONE pin = 1, then FPGA is configured after downloading the SPI interface core.

I also designed a similar board using XC6SLX45.

In this board, there is not any problem in programming SPI flash

Is it difference programming flash between XA series and XC series ?

Unlikely.

• Are there any differences in the status register bits between the two boards?
• Are there any differences in the schematics between the two boards?
• Does SPI erase command complete successfully?

-- Bob Elkind

[jembeng]

Thanks for reply

==> It seems that FPGA couldn't start-up after downloading 'xc6slx45_spi.cor'

If DONE pin = 1, then FPGA is configured after downloading the SPI interface core.

DONE pin = 1. I think that FPGA is configured but it didn't start-up.

I also designed a similar board using XC6SLX45.

In this board, there is not any problem in programming SPI flash

Is it difference programming flash between XA series and XC series ?

Unlikely.

• Are there any differences in the status register bits between the two boards?

 There are differences in the status register bits. GTS_CFG_B and GWE.

• Are there any differences in the schematics between the two boards

And there are no differences in the scematics but layouts are different.

• Does SPI erase command complete successfully?

FPGA did not try any SPI operation

[eteam00]

When using iMPACT to indirectly program an SPI flash memory, these are the process steps:

• iMPACT must first detect and identify the FPGA and the SPI flash memory connected to the FPGA.

• iMPACT will clear the FPGA configuration.

• iMPACT will configure the FPGA with a pre-designed "core".  This "core" is an SPI interface to the SPI flash memory.  Once the FPGA has been configured by iMPACT, the FPGA 'DONE' pin must be '1' before the SPI flash programming operation can begin.

• iMPACT will start a program or state machine in the FPGA to clear the SPI flash memory.  iMPACT does not communicate directly with the SPI flash memory, communication is indirect, using the FPGA as an intermediate interface controller.

• iMPACT must detect that the SPI flash memory has successfully been cleared.

• iMPACT then programs the SPI flash memory (indirectly).

• iMPACT then reads the programmed contents of the SPI flash memory to verify correct programming (indirectly).

None of this depends on the connections to the Spartan-6 M0 and M1 pins, to my understanding.  All FPGA programming is done through the JTAG interface, which over-rides the settings of the M0 and M1 pins.

Q.  If DONE pin = 1, then FPGA is configured after downloading the SPI interface core.

A.  ONE pin = 1. I think that FPGA is configured but it didn't start-up.

I was referring to the SPI interface core loaded into the FPGA by iMPACT, step #3 in the sequence described above.

Q.  Does SPI erase command complete successfully?

A.  FPGA did not try any SPI operation

I was referring to iMPACT erasing the SPI flash memory (indirectly), not the operation of the FPGA configuration which you designed.

-- Bob Elkind

[jembeng]

iMPACT console message is below for the two cases.

In the failure case, there is no operation after reading status register.

XA6SLX45

XC6SLX45

Selected part: M25P64 Unprotect sectors: FALSE INFO:iMPACT - Current time: 2012-04-21 ???? 1PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 25000000. Validating chain... Boundary-scan chain validated successfully. '1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations. INFO:iMPACT - Downloading core file C:/Xilinx/13.4/ISE_DS/ISE/spartan6/data/xc6slx45_spi.cor. '1': Downloading core...  LCK_cycle = NoWait. LCK cycle: NoWait done. '1': Reading status register contents... INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0010 0100 1100 1100 INFO:iMPACT:2492 - '1': Completed downloading core to device. è There are no operation after reading status register. INFO:iMPACT - '1': Flash was not programmed successfully.

Selected part: M25P64 Unprotect sectors: FALSE INFO:iMPACT - Current time: 2012-04-21 ???? PROGRESS_START - Starting Operation. Maximum TCK operating frequency for this device chain: 25000000. Validating chain... Boundary-scan chain validated successfully. '1': SPI access core not detected. SPI access core will be downloaded to the device to enable operations. INFO:iMPACT - Downloading core file C:/Xilinx/13.4/ISE_DS/ISE/spartan6/data/xc6slx45_spi.cor. '1': Downloading core...  LCK_cycle = NoWait. LCK cycle: NoWait done. '1': Reading status register contents... INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 1100 1110 1100 INFO:iMPACT:2492 - '1': Completed downloading core to device. '1': IDCODE is '202017' (in hex) '1': ID Check passed.  '1': IDCODE is '202017' (in hex). '1': ID Check passed.  '1': Erasing Device. '1': Using Sector Erase. '1': Programming Flash. '1': Reading device contents... done. '1': Verification completed. '1':Programming in x1 mode. '1': Programmed successfully. INFO:iMPACT - '1': Flash was programmed successfully.  LCK_cycle = NoWait. LCK cycle: NoWait INFO:iMPACT - '1': Checking done pin....done. '1': Programmed successfully.

[eteam00]

Have you already opened a webcase?

If you haven't already done so, it's time to do so.

There is a difference between the two devices with respect to M1 pin setting, but that doesn't explain the iMPACT failure.  I do not know the significance (if any) of the Global Write Enable and Global 3-State signals.

Bottom line, I don't know enough to help you.  Perhaps someone else might have better understanding.

When you sort this out, please post your results in this thread.

-- Bob Elkind

[burthashizume]

Please post what you found out and how to get the spi flash to program. I am having the IDENTICAL problem with a XC6SLX45T.

1. I can program the FPGA directly with the .bit file and the DONE signal is high.

2. iMPACT sees the FPGA and the SPI flash (Quad-IO SPI flash).

3. I can set the SPI flash as a N25Q32 part.

4. When I try to program the SPI flash, the SPI access core is successfully loaded ("INFO:iMPACT:2492 - '1': Completed downloading core to device.") but the next message is "INFO:iMPACT - '1': Flash was not programmed successfully." This is consistent and happens on multiple boards.

5. There is some sclk activity from the FPGA to the SPI flash, almost no activity on the MOSI-CSI_B signal, and no acitivity on the DIN-D0 signal.

Thanks for any help and insight to this problem.

Burt.

[burthashizume]

Solved my own problem.

A load on the DONE signal was dragging it down to an indeterminate state. fpga thought it was DONE but wouldn't release the INIT line. This stopped everything else. Disconnecting the external load fixed everything.

Burt.