Spartan® Family FPGAs

[eteam00]

Does replacing the Numonyx ST SPI flash memory with a "fresh" device resurrect the board?  If so, that would seem to narrow down the range of fault possibilities.

Downloading the M25P40 datasheets (from the Digikey website) for both Numonyx (Micron) and ST --

• The datasheets look very similar (formatting, table of contents, etc.)
• Both have the same "Manufacturer Identification" code in the RDID sequence
• ST shows 50MHz max serial clock freq, Numonyx is rated for 75MHz max. (don't think this is a problem, though)

I did not look very deeply for differences, though...

Does iMPACT auto-detect the attached SPI memory, or do you manually select the target memory?  Perhaps there is an error in the target device selection?  All 4Mbit SPI flash memories look alike, right?  (just guessing)...

-- Bob Elkind

[dspulator]

It appears that ST Microelectronics PROMs are also supported, if this is to be believed:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/isehelp_start.htm

See the last section on the page where it reads:

"...specify the location of the MCS, EXO, TEK, or HEX file for the selected SPI PROM (Numonyx (STMicro): M25P, M25PE, M45PE, Atmel: AT45DB, or Winbond: W25Q)"

[eteam00]

Where are R51 and R52 located on the board?  Next to the SPI flash memory or next to the FPGA?

What is the distance between the FPGA and the SPI flash memory?

Are any other SPI devices connected to the SPI signal lines?

-- Bob Elkind

[dspulator]

R51 and 52 are right up against the PROM, and the PROM is about 1 cm from the side of the FPGA where the PROM signals emanate.  It's as close as possible, and the routes are all direct and short.  I tried removing R51 and 52 also -- the recommended 50 ohm termination is a little stiff and reduces noise margin -- with no difference in this problem.  

There is a 2 ns overshoot and undershoot single spike on the clock with or without R51 and 52, amplitude 0.8 V with and 1.3 V without (measured with 1 pF 900 MHz FET probe).

No other SPI devices on the PROM SPI lines.

Gerrit

[dspulator]

Updates:

I cannot obtain Micron M25P40's for love nor money.  DigiKey and Avnet repeatedly send me ST parts, even though their part descriptions say Micron.  

I have tried two ST M25P40 and one ST M25PE40 on the same board now, same result: no PROM commands work.  Tried strapping the M25PE40 /RESET pin to system reset, no help.  Still seeing the PROM signals switching, but all actions fail in iMPACT.

Clock frequency to the PROM is 2.16 MHz, so I'm definitely not pushing the speed limit of the part.

I probed the power on the back side of the FPGA with the close-probing tip and could not see any noise at 20 mV/div (1 GHz Agilent scope, no BW limit).

I tried pushing down firmly on the FPGA while doing a PROM command, to see if there are any fab or soldering intermittents, and no change.

[dspulator]

More updates:

I removed the 2x 100 ohm terminator recommended by Xilinx on the PROM CK pin, carefully lifted the pin, and inserted a series 47 ohm 0603 resistor between the pad and the pin.  I close-probed this, and the waveform at the PROM pin is gorgeous -- the over and undershoot are gone, the signal levels are the full supply voltage, and the rise/fall times are 1.5 ns.  Then I lifted the Select and Data In pins and inserted 47 ohm resistors there too.  All three of these pins now have textbook-perfect waveforms on them, close-probed relative to the PROM ground pin.

And no change -- still can't perform any PROM operations from iMPACT.

[brimdavis]

> And no change -- still can't perform any PROM operations from iMPACT.

 The IMPACT Indirect SPI method depends upon the successful download and startup of an special Xilinx configuration bitstream, containing an JTAG-> SPI bridge, in order to operate properly.

 If this configuration bitstream does not start up properly, the symptoms are those that you describe - none of the IMPACT indirect SPI PROM operations will work.

Debug suggestions:

 - Have you tried with the MODE pins set to JTAG ?
   ( past families/IMPACT have had configuration conflicts between JTAG and master modes )

 - Is there an error message in the IMPACT log after the indirect core download?

 - Is the DONE pin going high after the IMPACT core has configured?

 - Is the DONE pin being loaded down by other circuitry not shown?
   - What is the actual voltage on DONE after the IMPACT SPI core has loaded?
   - Does the internal status register show both DONE bits active?

old comp.arch.fpga threads with more indirect/DONE debugging info:

2008 V5 Indirect SPI problem ( multi-FPGA DONE, MODE = JTAG )
  http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/2a291d5c38abbd3c

2009 post listing S3A/E JTAG mode conflict datasheet references:
  http://groups.google.com/group/comp.arch.fpga/msg/797303edfd4e7cac

2010 V5 DONE not going high ( DONE loaded down by bad LED driver )
  http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/d88991d794f687d7

 individual posts listing things to check:
  http://groups.google.com/group/comp.arch.fpga/msg/a9aa114cedf9d2d9
  http://groups.google.com/group/comp.arch.fpga/msg/add1060e3b0e00f5

Brian

[eteam00]

- Have you tried with the MODE pins set to JTAG ?
   ( past families/IMPACT have had configuration conflicts between JTAG and master modes )

There is no dedicated JTAG mode setting for the Spartan-6 M1:0 pins.  See UG380 Table 2-1.

-- Bob Elkind

[brimdavis]

>There is no dedicated JTAG mode setting for the Spartan-6 M1:0 pins

 Then switch to a mode like Slave Serial during the indirect configuration

attempt instead.

 The intent of that debug suggestion was to avoid any possible

bitstream conflicts ( SPI-master-config-already-started vs. JTAG )

that have been seen in previous families

Brian

[eteam00]

Then switch to a mode like Slave Serial during the indirect configuration attempt instead.

The intent of that debug suggestion was to avoid any possible bitstream conflicts ( SPI-master-config-already-started vs. JTAG ) that have been seen in previous families

There are no conflicts, Brian.  JTAG always wins.  After the indirect programming core is loaded into the FPGA, the FPGA is configured and -- as you accurately described in your previous post -- the FPGA's DONE pin will go HIGH.

Let's avoid red herrings or wild goose chases.  I have many board designs similar to Gerrit's board -- including Spartan-6 designs -- and indirect SPI programming works just fine with the M1:0 pins strapped to Master Serial/SPI mode.

There is something wrong which is not evident in the schematic which Gerrit posted at the top of this thread.

-- Bob Elkind