Spartan® Family FPGAs

[eteam00]

A recent thread asked this question:  'How many times can you re-program a Spartan device?', and the answer given was 'no limit, you can re-program them an infinite number of times.'

In theory, the answer which was given is correct.  As a design engineer, however, certain practical considerations demand our attention, and a practical real-world answer is deserved.

Assumptions:

Design engineer is 24 years old, has a life expectancy of perhaps 80 years old, but will burn out from active design work by the age of 57.  In other words, his (or her) interest in (personally) re-programming Spartan devices is likely to last no more than another 33 years.

Of those 33 years of active Spartan device programming, only during the first 5 years will this designer be single and working 7 days a week and an average of 12 hours per day.

Once the engineer (let's presume a non-child-bearing male, for the purposes of discussion) is married, work life is likely to slow down a bit -- to perhaps 5 days per week (on average) and only 10 hours per working day.

Some 14 years after marriage, the engineer's children will enter their teens.  This will undoubtedly cause great emotional distress and distraction which will hamper the design engineer's productivity and limit effective work time to perhaps 6 hours per day.  This lifestyle is likely to continue for roughly 6 years, when the kiddies have gone on to college (to train to be a designengineer, no doubt), or have left home to join the traveling circus.

With all the kids grown and out of the home (but not necessarily financially or emotionally self-supporting), design engineer productivity should expand (once again) to perhaps 8 hours per day (and still 5 days per work week).  This phase of the engineer's like begins roughly at age 49, and likely continues to the point at age 57 when one of the following is likely to happen:

• promotion to manager, in which case all further hands-on technical work immediately ceases.

• mid-life crisis confronting the futility and vanity of everything takes hold, and the design engineer leaves the technology industry field entirely to open a bicycle repair shop (or a small bookstore with a beverage bar).

Let's sum up this typical engineer's career:

 5 (single) years at 7x51 work days per year, 12 hours per day, for           21 420 total work hours

14 young-married years at 5x50 work days per year, 10 hours per day, for      35 000 total work hours

 6 teen-raising years at 5x48 work days per year, 6 hours per day, for         8 640 total work hours

 8 pre-disillusionment years at 5x48 work days per year, 8 hours per day, for 15 360 total work hours

The grand total number of career work hours is 80 420

Assume that in each work hour, you can (if you try in earnest) program a Spartan device as many as 45 times.

The answer to the question 'How many times can you re-program a Spartan device?' is, in fact, 3 618 900.  In other words, the correct answer is quite different from 'no limit, you can re-program them an infinite number of times.'  No, you cannot.  You will die of a heart attack from your sedentary fluorescent-lit office lifestyle long before then.

The practical limit for the number of times you can re-program a Spartan device is roughly 3,6 million.

-- Bob Elkind

[eilert]

Hi Bob,

so you identified humans to be the limiting factor.

But every problem has a solution (We are enginieers aren't we?):

   http://www.youtube.com/watch?v=YQLbwOGT8eM&feature=related

;-)

Cheers

  Eilert

[gszakacs]

But seriously folks, it is a valid question to ask how many times you can change the program in the EEPROM or Flash that configures the Spartan device, which in the case of Spartan 3AN is internal to the device package.  That number tends to be somewhat smaller, but still larger than most people would run into over the life of the product.

In another thread, the read life of the Device DNA came to light.  If your program reads the DNA once each time you reconfigure the FPGA, then it will eventually fail before you hit the 3.6 million mark.

Also the life of the power supply components in a system will likely limit the useful life of the board-level product and prevent you from programming the device before you hit the 3.6 million mark.

-- Gabor

[mcgett]

>  If your program reads the DNA once each time you reconfigure the FPGA, then it will eventually fail before you hit the 3.6 million mark.

The Spartan-6 DS162 data sheet has this specifcation as 30 million read cycles well above the 3.6 million that Bob calculated.  :-)   As a side note the 7 Series DNA/eFuse functionality was changed and there is no longer a limitation on the number of read cycles.

[eteam00]

But seriously folks

Uhhh...  buzz-kill, Gabor!

it is a valid question to ask how many times you can change the program in the EEPROM or Flash that configures the Spartan device, which in the case of Spartan 3AN is internal to the device package.  That number tends to be somewhat smaller, but still larger than most people would run into over the life of the product.

A typical spec for the NOR flash memory used in SPI memory devices is 100K erase/write cycles per page.

Also the life of the power supply components in a system will likely limit the useful life of the board-level product and prevent you from programming the device before you hit the 3.6 million mark.

If you consider that each reconfiguration involves the flexing of at least one finger joint for a button press, switch flip, or mouse click (and two flexes if you must clear the "Programming Completed" response box), then there are biological limits more worthy of consideration than decoupling capacitor power cycles (especially if you limit yourself to ceramic capacitors, or you maintain power to the board in order to maximise your FPGA re-configuration bandwidth).

For example, if each appendage is rated for at most 100 000 repetitive carpal-tunnel-syndrome-inducing flexes before you are legally eligible for a workmen's comp claim, a United Nations human-torture complaint, or complete joint failure disability claim (e.g. the finger falls off), then the practical limit is a mere 2 000 000 cycles -- even if you spread the mouse-clicks among all 10 fingers and 10 toes.  (note: this assumes no toes or fingers are missing, and that the typical engineer is born with no more than 20 fingers and toes, in any combination).

-- Bob Elkind

[ccon67]

We know 2 things the outer-universe is limitted, and FPGA is made of silicon :-))

Let say I have a hadware with an FPGA inside, that requires to turn on/off power every minute...So, how long will the unit last?

Assume it works for 24/7 and the power supply can last several hundreds years....Btw, check out this light bulb, it lasts just 110 years

http://en.wikipedia.org/wiki/Centennial_Light

[thomas1974]

I think the worst is partial reconfiguration done by the **bleep**AN / system itself within seconds. But anyway this does not lead to large numbers anyway.

So reprogramming itself should not be of any relevance, if one compares to DRAM-devices and their refresh cycles.

My suggestion is somewhat different: All silicon devices in principle suffer from many kind of long term degradation, depending on the interferences from the environment such as voltage, current, heat, and even light (maybe not from the bulb above, but UV from the sun.)  We know artifacts of SRAM devices caused by radiation and particle beams especially - and atom migration caused by ove rvoltage when trying overclocking SRAM modules. They might get permanently damaged. Long term degradation might also happen according to chemical processes in the silicon.

Now assuming the FPGA is run fine at the recommended operation conditions ( low voltage, low current), protected from light intruding it's transistor's junctions and also far away from particle beams and high power radiation, is their any degradation effect, one could expect?

[rcingham]

"is there any degradation effect one could expect?"

The silicon, dopant, and copper/aluminium atoms will all be vibrating, as the temperature is well above 0K. A (very small) proportion will break free.

If the temperature fluctuates, there will be cyclic mechanical stresses that will eventually cause fatigue failures.

NOTHING in this universe lasts forever...

[mcgett]

> is their any degradation effect, one could expect?

Everything degrades or wears out over time.   The specifications found in the product data sheets are guaranteed for the lifetimes specified in the qualification report for each FPGA family when the recommended operating conditions are met.

[thomas1974]

Should be interesting to keep an FPGA constantly at 84°C (standard temperature range border in european centigrades) at 1,8*1,1 V Die +  3,6 V VCCO (datasheet maximum) and reprogram it every minute in full sunlight (infrared photons and radioation) and compare it to other vendor's devices.

I know a company (part of EADS) offering missiles (wich have to stay ready to use for about 30 years!) which uses Xilinx FPGAs, while another one, which produces aircraft electronics (mil + civlil) totally uses ACTEL only because of beam resistance, while another one, producing electronics for particle beam accelerators uses Altera :-)