Spartan® Family FPGAs

[williedai]

Hi all,

I am working on Boundary-scan development of a customer's project. This board includes one Spartan-3AN FPGA (XC3S700AN -4F GG484I).The JTAG connector on the board is connected to the TAP signal pins of the FPGA. The TAP signals of other 3 boundary-scan devices on the board are connected to the I/O pins of the FPGA. The designer's idea is to use the FPGA to greate a JTAG mux and configure the FPGA to stitch all 4 devices into one chain.

Would it be possible to create this scan chain?

Any comments and suggestions would be appreciated!

Thanks,

Willie

[mcgett]

This is adding uncessary complication to the system and would require custom software to support it.  All of the devices should be in the same JTAG chain.

[williedai]

Thanks for your input, Mcgett!

I absolutely agree with you that this design makes the boundary-scan test much more complicated. But I have to find a way to develop the boundary-scan test for this board.

I use Corelis TPG (test Program generator) to generate JTAG test program. With this tool I can generate a test program by merging some FPGA pins to make one scan-chain. For example, U1 is the FPGA and U2 is another JTAG device connected to the FPGA I/O pins (actually 3 JTAG devices connected te FPGA pins). the TPG can generate a chain like this:

U1.A1 (U1's TDI to JTAG connector) -> U1.B2 (U1's IO pin) -> U2.C3 (U2's TDI) -> U2.D4 (U2's TDO) -> U1.E5 (U1's IO pin) -> U1.F6 (u1's TDO to JTAG connector).

Could the FPGA be routed as above and meet the boundary-scan requirements?

Willie

[mcgett]

> Could the FPGA be routed as above and meet the boundary-scan requirements?

It is not possible to directly connect the FPGA JTAG pins to user IO pins in the FPGA.   There is an internal access port for JTAG commands called BSCAN_SPARTAN3A (see UG332).   The documentation states that the TDI, TMS and TCK pins are accessible in the fabric, but the return TDO would only be used if a TAP controller had received a USER1 or USER2 instruction.

In theory it is possible to make the system work with enough FPGA design effort and modications to the Corelis TPG software that you are using, but the time and effort required may exceed the time and effort to fix the PCB.