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## Spartan® Family FPGAs

Xilinx Employee
Posts: 199
Registered: ‎07-30-2007

# Re: How to declare two bit input in UCF of verilog

[ Edited ]

You forgot the reg.  This works for me.  You will have to assign the one two three etc to the pin in the ucf.

module alu2bit(aluout,result,zero,one,two,three,four,five ,six,seven,eight,nine,a,b,select);
output [3:0] aluout,result; // the result
output reg zero;
output reg one;
output reg two;
output reg three;
output reg four;
output reg five;
output reg six;
output reg seven;
output reg eight;
output reg nine;
input [1:0] a,b; // input a and b
input [1:0] select;
reg [3:0] aluout,result;

always@(*)
begin
case (select)
2'b00:aluout=a+b; // For addition of two bits
2'b01:aluout=a-b; // For addition of two bits
2'b10:aluout=a*b; // For multiplication of two bits
endcase
zero <= (aluout==4'd0) ? 1'b1:1'b0;
one <= (aluout==4'd1) ? 1'b1:1'b0;
two  <= (aluout==4'd2) ? 1'b1:1'b0;
three <= (aluout==4'd3) ? 1'b1:1'b0;
four <= (aluout==4'd4) ? 1'b1:1'b0;
five <= (aluout==4'd5) ? 1'b1:1'b0;
six  <= (aluout==4'd6) ? 1'b1:1'b0;
seven <= (aluout==4'd7) ? 1'b1:1'b0;
eight <= (aluout==4'd8) ? 1'b1:1'b0;
end
endmodule

-R

Super Contributor
Posts: 136
Registered: ‎08-31-2010

# Re: How to declare two bit input in UCF of verilog

[ Edited ]

sir when i synthesize it i get the message

WARNING:Xst:1306 - Output <result> is never assigned.
WARNING:Xst:737 - Found 4-bit latch for signal <\$old_aluout_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

I have removed result as it is not used in code

after removing result i get this warning message

WARNING:Xst:737 - Found 4-bit latch for signal <\$old_aluout_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

then when i tell it to generate bit file i get this message

pic attached

THIS is UCF

NET "a<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; //for a input

NET "a<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; //for a input

NET "b<0>" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; // for b input

NET "b<1>" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; // for b input

NET "select<0>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; //for select input

NET "select<1>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; //for select input

NET "one" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "two" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "three" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "four" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "five" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "six" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "seven" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

NET "eight" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

Super Contributor
Posts: 136
Registered: ‎08-31-2010

# Re: How to declare two bit input in UCF of verilog

SIR bit file has been generated now

and let me check it

thanks sir for ur help

Xilinx Employee
Posts: 199
Registered: ‎07-30-2007

# Re: How to declare two bit input in UCF of verilog

I tried to fix the code given and I think it will work as is.  It would be more normal have a clock input and instead of

always @ (*);

use

always @(posedge clk);

Super Contributor
Posts: 136
Registered: ‎08-31-2010

# Re: How to declare two bit input in UCF of verilog

Respected Sir,

Thanks my Kit is working now and my problem is solved.

I am highly thankful to all other people who helped me

I was very much tired.

My sincere apologies if i said something harsh.

It is b/c of u people that i using this FPGA kit

Take care

and thanks to Sir Roym Again

Visitor
Posts: 8
Registered: ‎09-20-2010

# Re: How to declare two bit input in UCF of verilog

WARNING:Xst:737 - Found 4-bit latch for signal <\$old_aluout_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

This warning is pretty crucial.  If you look at this part of the code:

case (select)
2'b00:aluout=a+b; // For addition of two bits
2'b01:aluout=a-b; // For addition of two bits
2'b10:aluout=a*b; // For multiplication of two bits
endcase

"select" can have four values (2'b00, 2'b01, 2'b10 and 2'b11) and you've only told the system what to do for three of them.  Basically, it doesn't know what to do to "aluout" when "select" is 2'b11, so strange things might start happening.  I'd recommend fixing it.

Xilinx Employee
Posts: 199
Registered: ‎07-30-2007