08-03-2011 07:34 AM
We use indirect programming with a Spartan-6 and a 32MB SPI flash (S25FL032P).
It takes over 10 minutes to program the flash (and less than 1 second to load the FPGA with the bitfile from the flash).
We have successfully programmed the flash with a third party tool and a STAPL file. It is as long as with the Platform Cable USB II.
The bottleneck appears to be the FPGA core managing the flash programming.
Probing the SPI bus reveal a 1MHz clock with a serious amount of dead times.
This flash supports 4-bit programming up to 80MHz or 104MHz with single bit transfert.
I can't find any options in Impact nor ISE to improve programming speed.
CCLK is set to 26MHz and SPI bus width to 4. It definitely works for loading the FPGA from the flash but does not improve the flash programming speed.
Does anybody have any idea, tip, scoop or bad news about that?
08-03-2011 08:31 AM
Perhaps not. Before you can program the device, you have to erase it (perhaps only partially erase). From the Fine Datasheet, that seems to take quite a long time, although quite a lot less than 600 s.
Maybe the FPGA core doesn't poll the WIP bit very often.
"If it don't work in simulation, it won't work on the board."
08-03-2011 04:42 PM
What kind of FPGA flash core are you using ?
I've developed a high-performance custom controller for that type of flash. From what I've seen, erase operation is the slowest - it takes 100s of ms to erase a sector (the datasheet specifies a wide range of erase time). Although I cannot provide exact numbers, erasing and programming the entire 32MB SPI flash at high speed can take minutes.
08-04-2011 03:17 PM
You'd have to open a case with Xilinx to get an explanation on the 1 MHz SCK in the indirect programming core. That does seem very slow given the capability of the Flash. However, the source for that core is not public. It may be related to the fact that they are using the internal FPGA config clock, which can vary widely.
At Avnet, we found a huge improvement in Flash Programming time by switching to the Digilent HS1 JTAG cable. As an example, the Avnet Spartan-6 MicroBoard is programmed with a ~10MB MCS file (bitstream, MicroBlaze app, Web Server file system). The Xilinx Platform Cable USB-II at the default 12 MHz JTAG Clock in iMPACT 13.1 took 635 seconds to perform the indirect SPI programming operation. When we switched to the HS1 at the default 10 MHz JTAG Clock in iMPACT 13.1, the operation took 242 seconds. When we increased the HS1 JTAG Clock from 10 to 30 MHz in iMPACT, that dropped the time to 206 seconds. This is nearly a 3x improvement.
If you have a relationship with your local Avnet FAE assigned to cover Xilinx, they are all equipped with HS1 cables, and you could request a demo.