01-16-2012 03:51 AM - last edited on 03-29-2012 05:52 AM by chughes
I'm working on a project involving I2C(using Spartan 3E FPGA) to communicate with EEPROM. I'm quite confused on how to start. Can someone suggesta vhdl code for an I2C Master mode?
I really appreciate the help. Thanks
01-16-2012 04:19 AM - edited 01-16-2012 05:18 PM
I'm working on a project involving I2C(using Spartan 3E FPGA) to communicate with EEPROM. I'm quite confused on how to start. Can someone suggest a vhdl code for an I2C Master mode?
Search the web for "I2C core". If you are not yet familiar with I2C protocol, then learning about I2C should be your first effort. The Wikipedia article on I2C is a good start, with links to the I2C specification and related docs.
-- Bob Elkind
01-16-2012 06:33 AM
The I2C cores I've seen have all been way more complex than you need for something like
talking to a single EEPROM. Most support multiple masters, clock stretching, 10 bit addressing,
and usually have a slave as well as a master in the same core.
You can find out enough to roll your own I2C master from the EEPROM data sheet if all
you have on that I2C bus is the FPGA and the EEPROM. I've done this both with HDL (Verilog)
and using PicoBlaze (bit-banging in assembly language).
If you intend to have an embedded processor using EDK (MicroBlaze), there is an I2C
IP core that comes with the EDK.
It's also worth searching these forums for "I2C Master VHDL" because I believe there
are quite a few threads on this subject.