Spartan® Family FPGAs

[roymesi]

Hi,

I'm using the IODELAY2 feature in S6 and for some reason I'm not getting what I've designed.

I'm using a 200MHz clock used as my IOCLK0 signal (see UG381 IODELAY white paper), and since 200MHz are equal to 5000pS and I want a 50pS tap delay, I will divide it by 250 (see the code below for IDELAY VALUE).

Here's the generic map of the variables for the IODELAY:

IODELAY2_inst : IODELAY2
generic map (
COUNTER_WRAPAROUND 	=> "STAY_AT_LIMIT", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE          	=> "SDR", -- "SDR" or "DDR"
DELAY_src=> "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
IDELAY2_VALUE 		=> 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
IDELAY_MODE 		=> "NORMAL", -- "NORMAL" or "PCI"
IDELAY_TYPE 		=> "VARIABLE_FROM_ZERO", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"-- or "DIFF_PHASE_DETECTOR"
IDELAY_VALUE 		=> 250, -- Amount of taps for fixed input delay (0-255)
ODELAY_VALUE 		=> 0, -- Amount of taps fixed output delay (0-255)
SERDES_MODE 		=> "NONE", -- "NONE", "MASTER" or "SLAVE"
SIM_TAPDELAY_VALUE 	=> 20 -- Per tap delay used for simulation in ps
)

 Well, I'm not getting it.

2 strange things happen:

First, the delay tap is about 100pS and not 50pS as expected.

And second, after about 45 taps, it seems as no additional taps gives more delay.

For example, using the scope I'm sampling my signal and check for the delay. When giving 10 steps delay, I get a 1ns delay (so 1 step equal to 100pS and not 50pS as I want to), but when I give 45 or 60 or 80 (etc.) I get the same delay for 45 steps, as if it is stuck at this delay.

Any help will be granted. I'm stuck on this matter for weeks.

Thx,

Roy

IDELAY_VALUE => 250, -- Amount of taps for fixed input delay (0-255)

[eteam00]

Using UG381 v1.4,

Read I/O Delay Modes (page 71) description of VARIABLE_FROM_ZERO and VARIABLE_FROM_HALF_MAX modes.

Read I/O Delay Calibration and Reset section (page 72).

Read I/O Delay Modes (page 71) description of COUNTER_WRAPAROUND modes.

Bottom line is that calibration determines the clock period (or bit interval), and delay settings are limited to a range of a single clock cycle.

-- Bob Elkind

[roymesi]

Thanks for the reply, Bob.

Believe me I read it back and forth but there are still some things I cannot understand...

For instance, the VARIABLE_FROM_ZERO and VARIABLE_FROM_HALF_MAX modes - can you explain them in your own words?

And the calibration process, is it done once in a while, for calibrating the delay steps to be accurate? or this IS the delay process all about (I mean, the calibration is the delay process?)

Thanks.

[eteam00]

For instance, the VARIABLE_FROM_ZERO and VARIABLE_FROM_HALF_MAX modes - can you explain them in your own words?

I'll try, without even looking at the UG381 text.

The VARIABLE modes are identical in all respects but one.  Calibration is measuring the IO clock period in units of delay taps.  Because the IO clock period can change and because the delay characteristics of the IO delay block can drift with die temperate and voltage, re-calibration from time to time is a good idea.  RESET and calibration at power-up is required.

After calibration is completed, the maximum delay tap setting is established (the minimum is always 0) -- the maximum delay tap setting corresponds to a delay of one clock period (or one bit period) greater than a delay tap setting of 0.  If the delay tap is incremented to this maximum setting, and then incremented again, there are two possible results, depending on the IODELAY block attribute settings:

• the delay tap setting is 'wrapped' to 0
• the delay tap setting remains at the maximum which was established by calibration.
  

The difference between VARIABLE_FROM_ZERO and VARIABLE_FROM_HALF_MAX is the initial delay tap setting after calibration is completed.

Does this explanation help?

-- Bob Elkind

[roymesi]

Yes, thank you.

So the CAL command need not be issued all the time, just once in a while (and at power up and reset it's preffered also).

Can you explain the 'one bit period'? which bit is that? why one bit period is equal to the clock period?

And the IDELAY_VALUE  - what does that mean? is that the number of delay steps I want? In the white paper it is written: "defines the delay tap value for input delay mode"

So, if I set this register to be 250 and my clock is 200MHz, then my delay will be 20pS for tap? (5nS/250)

Thx again.

[eteam00]

Can you explain the 'one bit period'? which bit is that? why one bit period is equal to the clock period?

The bit period refers to what the input data signal -- which is being delayed in the IODELAY2 block -- represents.

Please consider why you are using an IODELAY2 block in your design.  Are you using it to delay an input signal?  If so, why are you delaying the input signal?

One of the intended uses of the IODELAY2 block is to change the timing relationship of an input signal with respect to a clock which is used to sample the input signal, to improve timing margins (setup and hold time) of the input signal with respect to the sampling clock at an input register.

The range of the delay adjustment in such an application does not need to be greater than a single clock period.  Delaying the input signal by 2.5 clock periods is effectively the same as delaying the input signal by 0.5 clock periods, resulting in the same setup and hold time (with respect to the sampling clock) in either case.

It is presumed, in such applications and use, that there is an integer multiple relationship between the sampling clock frequency and the input signal bit rate.  If this is not the case, then the input data signal is asynchronous with respect to the sampling clock, and there is no point in delaying the input signal.  Agreed?

So...  the calibrated input delay modes of the IODELAY2 are intended for synchronous data input signals.  In other words, there is a correspondence between the sampling clock period and the bit rate of the input data signal which is being delayed and sampled.  In my previous description, I equated the sampling clock period with the input signal bit period.  This is an oversimplification which is true for many -- but not all -- applications.

And the IDELAY_VALUE  - what does that mean? is that the number of delay steps I want? In the white paper it is written: "defines the delay tap value for input delay mode"

This term is described in UG381 Table 2-9.

So, if I set this register to be 250 and my clock is 200MHz, then my delay will be 20pS for tap? (5nS/250)

IDELAY_VALUE is an attribute, not a register.  It is not a IODELAY2 signal port.  Signal ports for IODELAY2 are summarised in UG381 Table 2-8.

IDELAY_VALUE is a fixed number which is specified at synthesis time when using the IODELAY2 block in FIXED mode.  You should re-read the summary of the the various usage modes on page 71 of UG381 (v1.4).

-- Bob Elkind

[roymesi]

Ok, thanks. got it now.

One more question though...

Can you explain in your own words the algorythm of the Delay line building block, as shown in figure 2-19 of UG381?

Even though it is explained, I did not understand (neither my co-workers...).

What is the role of the ring oscillator in this design? in simple words, does it determine the speed of the 5-bit counter?

what does a 3-bit ring oscillator mean? I know what is a ring oscillator, but not a 3-bit ring oscillator.

The 5-bit counter is preset by the five MSBs of the delay line value - what does that mean? if I start counting from, let's say, 8 to 31, so the five MSB's are preset at 8, so, what are the consequences? in my example, how can it loop from 0 to 31 (as stated at UG381) if the five MSBs are preset at 8 and it count till 31?

Please explain if you can...

Thank you!

[eteam00]

Can you explain in your own words the algorythm of the Delay line building block, as shown in figure 2-19 of UG381?

It's not worth the time and effort.  Figure 2-19 is a simplified diagram.  It is too simplified to deserve much critical attention.  Don't be distracted by this diagram, especially if it is confusing.

-- Bob Elkind

[roymesi]

Ok, so forget it...

Here's a simple question I could not find any reference to - how do i determine the resolution of a delay step? 

And please don't send me to a specific place in the data sheet, just explain in your own words.

:-)

Thanks.

[roymesi]

And more importantly, is the delay step is constant?
Where is any reference to it?